# MC9S08PA32 - SPI Problem

Question asked by Juanma Bailen on Nov 7, 2014
Latest reply on Nov 20, 2014 by rickli

Hi everybody! This is my first request. Sorry if I don't explain correctly ^^ I'm using a S08 microcontroller and I need to use the SPI communication.

The S08 works as slave. When the master sends a byte, the slave recieved and prepare a byte to answer at next master's clock. For example:

SS goes 0

1. Master sends 0x90 and Slave has 0x00 (not defined previous buffer). Slave prepares a 0x20 for next CLK.

2. Master sends 0x40 and Slave has 0x20 (step 1). Slave prepares a 0xAA for next CLK.

3. Master sends 0x01 and Slave has 0xAA (step 2). Slave prepares a 0xBB for next CLK.

4. Master sends 0x01 and Slave has 0xBB (step 3). Slave prepares a 0xCC for next CLK.

5. Master sends 0x01 and Slave has 0xCC (step 4). Slave prepares a 0xDD for next CLK.

6. Master sends 0x01 and Slave has 0xDD (step 5). Slave prepares a 0x55 for next CLK.

SS goes 1

.....Next TX

SS goes 0

7. Repeat step 1 with: Master sends 0x90 and Slave has 0x55 (previous buffer). Slave prepares a 0x20 for next CLK.

...And so on

SS goes 1

The problem is I need to wait 2 cycles for each byte. Here's the example:

SS goes 0

1. Master sends 0x90 and Slave has 0x00 (not defined previous buffer). Slave prepares a 0x20 for next CLK.

2. Master sends 0x40 and Slave has 0x00 (not defined previous buffer). Slave prepares a 0xAA for next CLK.

3. Master sends 0x01 and Slave has 0x20 (step 1). Slave prepares a 0xBB for next CLK.

4. Master sends 0x01 and Slave has 0xBB (step 2). Slave prepares a 0xCC for next CLK.

5. Master sends 0x01 and Slave has 0xCC (step 3). Slave prepares a 0xDD for next CLK.

6. Master sends 0x01 and Slave has 0xDD (step 4). Slave prepares a 0x55 for next CLK.

SS goes 1

.....Next TX

SS goes 0

7. Repeat step 1 with: Master sends 0x90 and Slave has 0x55 (previous buffer). Slave prepares a 0x20 for next CLK.

...And so on

SS goes 1

17.3.4 SPI Status Register (SPIx_S)

...

bit 5 > SPTEF > " For an idle SPI, data written to DH:DL is transferred to the shifter almost immediately so that SPTEF is set within two bus cycles, allowing a second set of data to be queued into the transmit buffer. "

I lost 1 cycle and I should the byte always at next TX