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Vybrid  Ballast Transistor + AN4807 Clarification

Question asked by Gordy Carlson Employee on Nov 6, 2014
Latest reply on Dec 18, 2014 by jiri-b36968

This inquiry directed to @Jiri Kotzian regarding AN4807 - Vybrid Power app note which he authored.


We are using an external switcher to supply the core power per the guidance of section 8.5 of the app note. The only difference is the BJT is being supplied from 1.8V instead of 1.5V in the app note.I believe the circuit in section 8.5 of the app note does not work in all cases, specifically when the 1.2V switcher voltage is less than what the internal LDO thinks the core voltage should be.

My questions specifically are:

  1.   Has Freescale or one of their customers successfully implemented the circuit shown in section 8.5 of the app note?
  2.   If so have they tested the case where the switcher supply is less than the internal LDO regulated voltage?

    3.   If yes is there something we are missing or have done incorrectly in our design or something we need to do internally in the processor to make this work (e.g. disable the BCTL signal)?  Besides the power issue I believe this may result in long-term damage (and a shortened life) of the part as I believe the current implementation is sourcing (significantly) more than the rated current out the BCTL signal.

  Attached is the schematic of that part of the circuit.  Other notes about our circuit and our observations below.

V1P2_GPP is connected directly to the GPP’s ( General Purpose Processor) core power input.

V1P2 is a switching power supply.

V1P2_SW_PWR_EN and V1P2_LDO_PWR_EN are connected to (3.3V) GPIOs on the Vybrid.

V1P2_BCTRL is connected to the Vybrid’s BCTL pin.

Our switcher output voltage is slightly lower than what the processor regulates to when using the LDO with the external BJT. When we move over to the switcher the BCTRL signal still seems to be trying to regulate the core supply. Because the switcher voltage is below what the LDO thinks it should be it drives (or tries to drive) the BCTRL signal to the rail (which seems to be 3.3V). This then seems to be backfed through the BJT to the 1.8V rail.

With the part installed I measure 1.8V at the collector, 1.8V at the emitter and ~2.6V at the base.

When I remove the part (after the processor has booted and moved to the switcher) I measure 1.8V at the collector, <100mV at the emitter, and ~3.2V at the base.

When I remove the part I see the 3.3V supply power drop by ~100mW, 1.8V power supply increase by ~30mW, and the overall power drop by ~50mW (so ~20mW is going somewhere else, I suspect the core rail itself).

This seems to be a fundamental issue with the design presented in the app note. (which I believe is implemented as presented in our design).