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Issue about SSI setting (I2S Master mode) in i.MX6Dual

Question asked by Keita Nagashima on Nov 6, 2014
Latest reply on Jan 23, 2015 by Keita Nagashima

Dear Sir or Madam,

 

Customer's board happened below issue.

 

[Status]

Device: i.MX6D

BSP: Yocto L3.10.17

Board: Custom board

SSI: I2S Master mode

Output: 4ch data output with network mode as normal bit clock + frame

ideal Frame Rate=44.1kHz

 

[Issue]

Phenomenon: Sound noize from both of Left and Right

Contents: 4ch Wav file(Left-ch:beep sound, Other 3-ch: No sound)

Detail:

- Refer to attached waveform. It looks LRCLK raise up early for 1ch interval.

- This phenomenon was confirmed on SABRE-SDP with custom setting, too.

 

[Register setting]

Refer to i.MX 6Dual/6Quad Applications Processor Reference Manual(p.5122) "Table 61-7. SSI Bit Clock and Frame

 

Rate as a Function of PSR, PM, and DIV2"

 

SSI's sys clock=11.2896MHz, DIV=0, PSR=0, PW=1, WL=7, DC=3

- SSI

 scr=0xbb                // TCH_EN = 0

 sier=0x1b80f00

 stcr=0x2ed             // TFEN0 = 1, TFEN1 = 0

 srcr=0x2cd             // RFEN0 = 1, RFEN1 = 0

 stccr=0xe201

 srccr=0xe201

 sfcsr=0x880688

 stmsk=0xfffffff0

 srmsk=0xfffffff0

 

- port1(Internal Port)

 ptcr=0x800

 pdcr=0xa000

 

- port6(External Port)

 ptcr=0x84010800

 pdcr=0x0

 

[Question]

Q1:

Do you find this cause?

Please give me some advice?

 

Q2:

Refer to below description.

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61.2.1 Signals Overview

SRCK

Serial Receive Clock. SRCK can be used as either an input or an output. This clock signal is used by the receiver

in asynchronous mode and is always continuous. During S, the STCK port is used instead for clocking in data. In

SSI synchronous modes, this port can be used as an output for the network clock (oversampling clock) . In I2S

master mode, this signal can be used to output the network clock to an external CODEC.

----------------------------------------------------------------------------------------------------

 

I consider that AUD6_RxC(equivalent to SRCK) doesn't have to connect.

Is it right in the following connection?

 

[Customer's connection]

BCLK(AUD6_TxC)

LRCLK(AUD6_TxFS)

DACDAT(AUD6_TxD)

MCLK(AUD_MCLK)

 

 

I attached more detail information.

Please check it, too!

(See attached file: (Detail)Waveform of Audio Codec)

 

Best Regards,

Keita

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