I am trying to debug a problem in our product based on Kinetis K70 (revision 3) and MQX 4.1.
This is what I am doing -
1. Write N bytes to a memory location in external memory (DDR) or program flash (upper half)
2. Flush and invalidate the data cache line of just written memory using _DCACHE_FLUSH_MBYTES( addr, N ) and _DCACHE_INVALIDATE_MBYTES( addr, N )
2. Calculate CRC of just written memory (using the hardware CRC peripheral or a SW CRC implementation)
3. Compare calculated CRC with expected CRC, it is incorrect
If I disable data caching, the CRC is correct every time. This is obviously a cache coherency issue. Are there any silicon bugs in the Kinetis family that I need to workaround? Disabling caching is not an option at all as the performance hit is unacceptable.
Thanks for your help.
Message was edited by: Shreyas Balakrishna Corrected typo