regarding to the AN4784 (http://cache.freescale.com/files/32bit/doc/app_note/AN4784.pdf) you have a "Maximum transition eye voltage: 0.376 volts". The boundary values to pass this testcase are ''257.000 mV < x < 600.000 mV".
I have a couple of questions, pls feel free to answer them:
- Did you use the half swing option of the transmit margin (PCIE_RC_LCSR2) ?
- How can you reach approx +0.4V/-0.4V ?
- How does the Supply of the PCIe_VPTX voltage look like?
- Did you supply the the PCIe Phy from the internal regulators of the imx6S (VDD_SOC)?
- Have you used a imx6S with 800MHz PLL (ARM_Clock)?
- Does you fullfill the compliance test, if a 1GHz version of the imx6s would be used?