I was working on vybrid internal l2 switch driver (fsl_l2_switch).
As expected the driver loaded successfully and switch functionality worked, but the switch driver makes the CPU load to ~100 percent.
After debugging the driver found that the 'schedule_timeout' function used in the thread had 1 jiffie (HZ/100). ~10 milli second.
Why is it required to poll the learning record valid bit (FEC_ESW_LSR) .... so frequently ?