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iMX6DL : How to set the PCIe PHY Reference Clock  source ?

Question asked by koichi sakagami on Oct 30, 2014
Latest reply on Nov 12, 2014 by koichi sakagami

Dear community,

 

I consider using i.MX6DL PCIe PHY
Please see Table 50-1 (p.4455) in IMX6SDLRM (Rev.1).

I hope use the  CLK1(In)  to "Reference Clock" as a clock source
with the following setting.

Is my understanding correct ?

 

CCM_ANALOG_PLL_ENETn (pp.909-911)
  ENABLE_100M:0x1
  BYPASS_CLK_SRC:0x1
  BYPASS:0x1

 

PMU_MISC1n (pp.4528-4530)
  LVDSCLK1_IBEN:0x1
  LVDSCLK1_OBEN:0x0

PCIE_PHY_MPLL_ASIC_IN (pp.4470-4471)
  MPLL_MULTIPLIER:0x19

PCIE_PHY_ATEOBRD_STATUS (pp.4474-4475)
  REF_CLKDIV2_IN:0x0

 

If some adittional setting is required, could you let me know it ?

 

Best Regards,
Koichi Sakagami

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