DDR3 Byte Group with i.MX6 Solo

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DDR3 Byte Group with i.MX6 Solo

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ko-hey
Senior Contributor II

Hi

I am designing a system with i.MX6 Solo processor with DDR3 32bit(16bit x2).

Hardware Development Guide in P43, there are following described.

"i.MX 6Solo only uses the first two pairs of the 2 Bytes groups."

Which does "the first two pairs" point in Figure 3-11? DDR TOP RIGHT and DDR BOTTOM RIGHT?

http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf

Please clarify,

Sincerely

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Yuri
NXP Employee
NXP Employee

IMX6 Solo DRAM memory controller (MMDC) supports only 32-bit data bus.
One can look at i.MX6 SDB / SDP design, where i.MX6 DRAM_D0-D15 are connected
to “Top right” DDR part and i.MX6 DRAM_D16-D31 are connected to “Bottom” one
(under the “Top right” part).  

Have a great day,
Yuri

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Yuri
NXP Employee
NXP Employee

IMX6 Solo DRAM memory controller (MMDC) supports only 32-bit data bus.
One can look at i.MX6 SDB / SDP design, where i.MX6 DRAM_D0-D15 are connected
to “Top right” DDR part and i.MX6 DRAM_D16-D31 are connected to “Bottom” one
(under the “Top right” part).  

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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ko-hey
Senior Contributor II

Yuri

Thanks!

I understood.

ko-hey

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