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MPC8569E increase flash memory, Uboot not working.

Question asked by Manavdeep Grewal on Oct 26, 2014
Latest reply on Nov 17, 2014 by Scott Wood

I have with me an MPC8569E based board. It is using 2 chips for flash memory, both of 128Mb, effectively the size of flash being 256Mb.

So the current Memory map of flash is :

0xF000_0000 to 0xFFFF_FFFF,

consisting of 2 banks (0xF000_0000 to 0xF7FF_FFFF and 0xF800_0000 to 0xFFFF_FFFF)

 

The corresponding entries in Uboot files are:

file: include/configs/MPC8569MDS.h

#define CONFIG_SYS_CCSRBAR0xE0000000/* relocated CCSRBAR */

#define CONFIG_SYS_FLASH_BASE            0xF0000000

#define CONFIG_SYS_FLASH_BASE2          0xF8000000    /* Second flash bank of 128MB */

#define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE

#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}

/*Chip select 0 - Flash 2*/

#define CONFIG_FLASH_BR_PRELIM          0xF8001011

#define CONFIG_FLASH_OR_PRELIM          0xF8006FF3

/*Chip select 1 - Flash 1*/

#define CONFIG_FLASH_BR1_PRELIM         0xF0001011

#define CONFIG_FLASH_OR1_PRELIM         0xF0006FF3

file: board/freescale/mpc8569mds/law.c

SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_512M, LAW_TRGT_IF_LBC),

file: board/freescale/mpc8569mds/tlb.c

SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,

               MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

               0, 0, BOOKE_PAGESZ_256M, 1),

 

Our requirement is to increase the flash Memory from 256Mb to 512Mb.

So now instead of 2x128Mb chips I am going to use 2x256Mb chips

The new memory map is thus:

0xE000_0000 to 0xFFFF_FFFF,

consisting of 2 banks (0xE000_0000 to 0xEFFF_FFFF and 0xF000_0000 to 0xFFFF_FFFF)

 

The corresponding modifications i made in Uboot files are:

file: include/configs/MPC8569MDS.h

#define CONFIG_SYS_CCSRBAR0xD0000000/* relocated CCSRBAR again */

#define CONFIG_SYS_FLASH_BASE            0xE0000000

#define CONFIG_SYS_FLASH_BASE2          0xF0000000    /* Second flash bank of 128MB */

 

*Chip select 0 - Flash 2*/

#define CONFIG_FLASH_BR_PRELIM          0xF0001011

#define CONFIG_FLASH_OR_PRELIM          0xF0006FF3

/*Chip select 1 - Flash 1*/

#define CONFIG_FLASH_BR1_PRELIM         0xE0001011

#define CONFIG_FLASH_OR1_PRELIM         0xF0006FF3

 

I don't find any need to change tlb.c or law.c keeping in view the entries used previously.

 

Now when I boot the board I get the following:

U-Boot 2009.11 (Oct 26 2014 - 12:58:32)

 

 

CPU:   8569E, Version: 2.1, (0x80880021)

Core:  E500, Version: 5.1, (0x80211051)

Clock Configuration:

       CPU0:1066.667 MHz,

       CCB:533.333 MHz,

       DDR:400  MHz (800 MT/s data rate) (Asynchronous), LBC:66.667 MHz

       QE:533.333 MHz

L1:    D-cache 32 kB enabled

       I-cache 32 kB enabled

Board: 8569 SCM MCP

I2C:   ready

DRAM:  Initializing

0 kB left unmapped

DDR:  2 GB (DDR3, 64-bit, CL=6, ECC off)

FLASH: Bad trap at PC: 7ff49458, SR: 21200, vector=d00

NIP: 7FF49458 XER: 20000000 LR: 7FF4941C REGS: 7febfd48 TRAP: 0d00 DAR: E0000000

MSR: 00021200 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00

 

 

GPR00: 000000F0 7FEBFE38 7FEBFF58 7FFC4230 000000F0 7FEBFE3F 000000F0 00000000

GPR08: 7FEBFE2C 000000F0 00000000 E0000000 00000006 2692A314 7FF88C00 7FFC0000

GPR16: 8A000422 8946C19B 1704812A 88700586 00001000 7FEBFD38 00000000 7FF4109C

GPR24: 7FEBFEF0 E0000000 7FF7517C E0000000 00000000 7FFC4230 7FF89104 E0000000

Call backtrace:

7FF4941C 7FF498E8 7FF4A6CC 7FF4ADC4 7FF42A14 7FF41630

Exception in kernel pc 7ff49458 signal 0

 

 

What am I missing here?

Outcomes