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Question, i.MX6SDL DDR_INPUT setting for DDR3

Question asked by AVNET JAPAN FAE (team share account) on Oct 24, 2014
Latest reply on Oct 24, 2014 by Yuri Muhin

Dear team,


I would like to ask about DDR_INPUT mode setting for MMDC signals.

Could you show me which of ‘CMOS input mode’ and ‘Differential’ should be set into DDR_INPUT in the case of using DDR3?

My customer believed that single-ended signals of DDR should be set to CMOS input mode, but it seems to be set to Differential in U-Boot code.

Should the DDR_INPUT of those single-ended signals, such as DRAM_DATAxx, be set to ‘Differential input mode’?