Hi, we wan't to receive longer frames via SPI slave, 16-32 bytes, without CS change.
How this can be done?
According to our tests:
- SPI interrupts are generated after CS goes inactive, means RX FIFO (4 bytes) override or lost some bytes,
- polling status works the same, flags are only set after CS goes inactive,
- disabling CS pin function disables receiving completely, no interrupts are generated and no status flags are set.
We are using MK10DX128VLH7 and SPI0, Kinetis Design Studio with processor expert.
We didn't succeed with setting DMA for receiving yet, but probably works the same?
BTW, documentation is not clear whether this chip has one or two SPI modules, e.g. no SPI1_SCK pin in reference manual rev.1.1 Dec 2012.