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How  I add another ADC channel on DMA that set on example?

Question asked by Kwon YM on Oct 14, 2014
Latest reply on Oct 19, 2014 by jeremyzhou

Hi, I use Differential ADC0 of DMA.

It used by example code.

But I don't know about how I add ADC1 channel that set on DMA.

I have been added ADC1 to code that use example.

but, result wasn't input on ADC1

 

About ADC0, It is on example.

About ADC1, It is my code.

 

//**** PDB config **********************************************************

  PDBCH0TRG0_Init (PDB_PRETRG_ON_DEALYED_CONFIG, 0x0010);

  //PDBCH0TRG1_Init (PDB_PRETRG_ON_DEALYED_CONFIG, 0x0010);

  PDB_Init (PDB_MODULE_SWTRG_NO_IRQ_CONFIG( PDB_PRESCALER_1, PDB_MULT_1, 0x1000, 0xFFFF), 1, NULL);

 

  //**** ADC config **********************************************************

  //**** ADC calibrations **************************************************

  ADC_ExecCalib (ADC0,ADC_MODULE_16B_IREF_HWTRG_CONFIG_U, &ram_adc0);       //DC OK, AC??

  //ADC_ExecCalib (ADC1,ADC_MODULE_16B_IREF_HWTRG_CONFIG_U, &ram_adc1);       //DC OK, AC??

 

  //**** ADC0,ADC1 initialization ******************************************

  ADC_Init  (ADC0, ADC_MODULE_16B_HWTRG_DMA_IREF_USER_CONFIG, ADC_CH_DI_POLL_CONFIG(DAD0), ADC_CH_DI_POLL_CONFIG(DAD0), 2, NULL);

  //ADC_Init  (ADC1, ADC_MODULE_16B_HWTRG_DMA_IREF_USER_CONFIG, ADC_CH_DI_POLL_CONFIG(DAD3), ADC_CH_DI_POLL_CONFIG(DAD3), 3, NULL);

 

  //**** DMA channel 0 *****************************************************

  DMACH0_CH1_Init();

  //DMACH1_CH1_Init();

  //**** Enable all interrupts ***********************************************

 

  EnableInterrupts;

  //**** Start PDB ***********************************************************

  PDB0_Trigger();

 

void DMACH0_CH1_Init(void)

  //****************************************************************************
  //**** DMA channel 0, use for Write ADC mux channel, form SRAM to ADC ********        101page datasheet
  //****************************************************************************
  DMAMUX0_CHCFG0           = DMAMUX_CHCFG_ENBL_MASK|DMAMUX_CHCFG_SOURCE(54);   //DMA source DMA Mux
  DMA_TCD0_SADDR          = (uint32) &uc_adc0_mux[0];                            //New mux setiing
  DMA_TCD0_SOFF           = 0x01;                                               //Source address increment, adding "1"
  DMA_TCD0_SLAST          = (uint32) -3;                                        //Source address decrement after major loop complete
  DMA_TCD0_DADDR          = (uint32) &ADC0_SC1A;                                //Destination address ADC0 mux selector
  DMA_TCD0_DOFF           = 0x00;                                               //Destination address increment, adding "0"
  DMA_TCD0_DLASTSGA       = 0x00;                                               //Destination address shift, go to back to [0]
  DMA_TCD0_NBYTES_MLNO    = 0x01;                                               //No of bytes minor loop
  DMA_TCD0_BITER_ELINKNO  = 0x03;                                               //Major loop step, 3 ADC channel are scaning
  DMA_TCD0_CITER_ELINKNO  = 0x03;                                               //Major loop step, 3 ADC channel are scaning
  DMA_TCD0_ATTR           = DMA_ATTR_SSIZE(0)|DMA_ATTR_DSIZE(0);                //Source a destination size, 8bit
  DMA_TCD0_CSR            = 0x0000;                                             //
 
  //****************************************************************************
  //**** DMA channel 1, use for Read ADC result data, form ADC to SRAM *********
  //****************************************************************************
  NVIC_SetIsr(INT_DMA1_DMA17,2);                                                      //17

  DMAMUX0_CHCFG1           = DMAMUX_CHCFG_ENBL_MASK|DMAMUX_CHCFG_SOURCE(40);   //DMA source ADC0
  DMA_TCD1_SADDR          = (uint32) &ADC0_RA;                                  //Source address ADC0 result register
  DMA_TCD1_SOFF           = 0x00;                                               //Source address increment, adding "0"
  DMA_TCD1_SLAST          = 0x00;                                               //Source address decrement after major loop complete
  DMA_TCD1_DADDR          = (uint32) &i_adc0_result[0];                         //Destination address, ADC0 result buffer
  DMA_TCD1_DOFF           = 0x02;                                               //Destination address increment, adding "+2"
  DMA_TCD1_DLASTSGA       = (uint32) -6;                                       //Destination address decrement after major loop complete
  DMA_TCD1_NBYTES_MLNO    = 0x02;                                               //No of bytes minor loop, 16bit ADC result
  DMA_TCD1_BITER_ELINKNO  = (DMA_BITER_ELINKNO_ELINK_MASK|0x0000|0x03);         //Channel 0 Link, Channel 0, Major loop step 3 x 4 = 12
  DMA_TCD1_CITER_ELINKNO  = (DMA_CITER_ELINKNO_ELINK_MASK|0x03);                //Channel 0 Link, Major loop step 3 x 4 = 12
  DMA_TCD1_ATTR           = DMA_ATTR_SSIZE(1)|DMA_ATTR_DSIZE(1);                //Source a destination size, 16bit
  DMA_TCD1_CSR            = (DMA_CSR_MAJORLINKCH(0)|DMA_CSR_MAJORELINK_MASK)|   //Major loop finished start request for Channel 0
                            DMA_CSR_INTMAJOR_MASK; //|DMA_CSR_INTHALF_MASK;     //Irq. enable, full transfer, half complet transfer
  DMA_ERQ                |= DMA_ERQ_ERQ1_MASK;                                  //HW request enable

}

void DMACH1_CH1_Init(void)

  //****************************************************************************
  //**** DMA channel 0, use for Write ADC mux channel, form SRAM to ADC ********        101page datasheet
  //****************************************************************************
  DMAMUX1_CHCFG0           = DMAMUX_CHCFG_ENBL_MASK|DMAMUX_CHCFG_SOURCE(55);   //DMA source DMA Mux
  DMA_TCD2_SADDR          = (uint32) &uc_adc1_mux[0];                            //New mux setiing
  DMA_TCD2_SOFF           = 0x01;                                               //Source address increment, adding "1"
  DMA_TCD2_SLAST          = (uint32) -3;                                        //Source address decrement after major loop complete
  DMA_TCD2_DADDR          = (uint32) &ADC1_SC1A;                                //Destination address ADC0 mux selector
  DMA_TCD2_DOFF           = 0x00;                                               //Destination address increment, adding "0"
  DMA_TCD2_DLASTSGA       = 0x00;                                               //Destination address shift, go to back to [0]
  DMA_TCD2_NBYTES_MLNO    = 0x01;                                               //No of bytes minor loop
  DMA_TCD2_BITER_ELINKNO  = 0x03;                                               //Major loop step, 3 ADC channel are scaning
  DMA_TCD2_CITER_ELINKNO  = 0x03;                                               //Major loop step, 3 ADC channel are scaning
  DMA_TCD2_ATTR           = DMA_ATTR_SSIZE(0)|DMA_ATTR_DSIZE(0);                //Source a destination size, 8bit
  DMA_TCD2_CSR            = 0x0000;                                             //
 
  //****************************************************************************
  //**** DMA channel 1, use for Read ADC result data, form ADC to SRAM *********
  //****************************************************************************
  NVIC_SetIsr(INT_DMA3_DMA19,3);                                                      //17

  DMAMUX1_CHCFG1           = DMAMUX_CHCFG_ENBL_MASK|DMAMUX_CHCFG_SOURCE(41);   //DMA source ADC1
  DMA_TCD3_SADDR          = (uint32) &ADC1_RA;                                  //Source address ADC0 result register
  DMA_TCD3_SOFF           = 0x00;                                               //Source address increment, adding "0"
  DMA_TCD3_SLAST          = 0x00;                                               //Source address decrement after major loop complete
  DMA_TCD3_DADDR          = (uint32) &i_adc1_result[0];                         //Destination address, ADC0 result buffer
  DMA_TCD3_DOFF           = 0x02;                                               //Destination address increment, adding "+2"
  DMA_TCD3_DLASTSGA       = (uint32) -6;                                       //Destination address decrement after major loop complete
  DMA_TCD3_NBYTES_MLNO    = 0x02;                                               //No of bytes minor loop, 16bit ADC result
  DMA_TCD3_BITER_ELINKNO  = (DMA_BITER_ELINKNO_ELINK_MASK|0x0000|0x03);         //Channel 0 Link, Channel 0, Major loop step 3 x 4 = 12
  DMA_TCD3_CITER_ELINKNO  = (DMA_CITER_ELINKNO_ELINK_MASK|0x03);                //Channel 0 Link, Major loop step 3 x 4 = 12
  DMA_TCD3_ATTR           = DMA_ATTR_SSIZE(1)|DMA_ATTR_DSIZE(1);                //Source a destination size, 16bit
  DMA_TCD3_CSR            = (DMA_CSR_MAJORLINKCH(0)|DMA_CSR_MAJORELINK_MASK)|   //Major loop finished start request for Channel 0
                            DMA_CSR_INTMAJOR_MASK; //|DMA_CSR_INTHALF_MASK;     //Irq. enable, full transfer, half complet transfer
  DMA_ERQ                |= DMA_ERQ_ERQ3_MASK;                                  //HW request enable

}

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