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Vybrid L2 cache latency settings?

Question asked by JEREMY SOMMER on Oct 9, 2014
Latest reply on Dec 2, 2015 by Stefan Agner

Hello,

I've noticed that the L2 cache latency settings for Vybrid have changed between kernels 3.0 and 3.13 as provided by Timesys, but using source evidently from Freescale.

The relevant source snippets are shown below.

 

File arch/arm/mach-mvf/mm.c in 3.0 kernel (from Timesys repo linux-mx.git, version 3.0-mvf):

 

int mxc_init_l2x0(void)

{

        ...

                writel(0x132, MVF_IO_ADDRESS(L2_BASE_ADDR + L2X0_TAG_LATENCY_CTRL));

                writel(0x132, MVF_IO_ADDRESS(L2_BASE_ADDR + L2X0_DATA_LATENCY_CTRL));

        ...

}

 

File arch/arm/boot/dts/vf610.dtsi in 3.13 kernel (from Timesys repo linux-mx.git, version 3.13-vf610-twr):


In arch/arm/boot/dts/vf610.dtsi:

            L2: l2-cache@40006000 {

                                compatible = "arm,pl310-cache";

                                reg = <0x40006000 0x1000>;

                                cache-unified;

                                cache-level = <2>;

                                arm,data-latency = <1 1 1>;

                                arm,tag-latency = <2 2 2>;

                        };

 

As you can see, the data RAM read and setup latencies have decreased from 3 to 1, and 2 to 1, respectively;  the tag RAM write latency has increased from 1 to 2, and its read latency has decreased from 3 to 2.  I noticed this when I discovered that my TWR-VF65GS10 would always experience 3.13 kernel startup hang when configured for an A5 core clock of 500 MHz (or even 452 MHz), whereas the 3.0 kernel starts up fine at those speeds.  I experimentally bumped the latencies up from "arm,data-latency = <1 1 1>; arm,tag-latency = <2 2 2>;" to "arm,data-latency = <2 2 2>; arm,tag-latency = <3 3 3>;" and this solved the problem.  Then I dug deeper, and saw the changes shown above.

 

Is there any guidance from Freescale as to what latencies should be used to guarantee successful operation at 500 MHz A5 core clock?  Similarly, is there any explanation for why these numbers changed?  (A possible answer would be "we wanted to optimize the device tree settings for users of our 400 MHz parts", etc.)  However, it seems to me it would be good to get this documented.

I have searched the Freescale and Timesys websites, and the web in general, to no avail.

Thank you,

-Jeremy Sommer

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