The RM's for the SDL and DQ state in chapter 12.3.3 that the size of the L2 cache of the DQ is 1 MB and that of the SDL is 512 KB, but as comment it states: "Size is implied by the Cache-Size times cache-ways".
However, both SDL and DQ RMs tables state 64 KB for cache way size and both state they have 16 ways. This would mean both SDL and DQ have 64 * 16 = 1MB of L2 cache.
Table 12-5 is contradicting itself. Which row is containing the wrong information?
Chapter 1.4 "Features" also states the SDL and DQ L2 cache sizes are different. However, the text in this chapter is also contradictory... The SDL RM first states "512 KB unified I/D L2 cache", but a couple of lines lower (under the heading "The memory system consists...") it states "Level 2 Cache—Unified instruction and data (256 KB)" (whereas the DQ RM has 1MB in both locations of chapter 1.4).
So, does the SDL have 1 MB (determined from 1st two rows of table 12-5), 512 KB (last row of table 12-5 and beginning of section 1.4) or 256 KB (couple of lines lower in section 1.4)?
Best guess is that the SDL has 8 ways of 64 KB cache, but maybe this is 16 ways of 32 KB cache?
Would be great to get that cleared up, thanks.