i.MX28 Detect voltage stabilization

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

i.MX28 Detect voltage stabilization

Jump to solution
946 Views
lategoodbye
Senior Contributor I

Hi,

i'm currently working on a Mainline Linux driver for the linear regulators of the i.MX28.

I've found out that the driver in the FSL BSP 2.6.35 uses the bit 9 (DC_OK) in HW_POWER_STS register to detect the voltage stabilization of dc control loop. But according to reference manual (page 935) this is only correct for voltage increase not for decrease.

Now i want to know, how to "make it the right way". First i thought of the HW_POWER_CTRL register with DC_OK_IRQ. But i want to be sure, that the interrupt comes for voltage increase AND decrease.

Additionally i need a timeout in milliseconds or microseconds, which defines the maximum time for voltage stabilization with enabled voltage steping. I didn't find any information about that in the datasheet.

Thanks in advance

Stefan

Labels (1)
Tags (3)
0 Kudos
1 Solution
701 Views
igorpadykov
NXP Employee
NXP Employee

Hi Stefan

yes limitation the same.

Best regards

igor

View solution in original post

0 Kudos
5 Replies
701 Views
fabio_estevam
NXP Employee
NXP Employee

Hi Stefan,

You should not worry about the voltage stabilization in the decrease path. Only the increase path is critical. For example: you need a minimum voltage level for a certain peripheral to operate. The 'decrease' path is not critical because usually an increased voltage means that you will only consume more power, but the device still operates correctly.

701 Views
lategoodbye
Senior Contributor I

thanks a lot

Stefan

0 Kudos
701 Views
igorpadykov
NXP Employee
NXP Employee

Hi Stefan

you are right, RM (page 935) describes this is as correct for voltage increase not for decrease,

but only for LDO case. For DC-DC it is correct in both directions, below part of  MCIMX28RM  p.935 :

"High when switching DC-DC converter control loop has stabilized after a voltage target change. When linear

regulators are active, this bit goes high when the actual voltage is above the target voltage. Therefore,

DC_OK will go high when changing a linear regulator output to a lower value before the actual voltage

decreases to the new target value."

Regarding timeout for voltage stabilization - this depends on loads (number of capacitors, load current),

that is depends on particular design.

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

0 Kudos
701 Views
lategoodbye
Senior Contributor I

Hi igor,

thanks. Regarding timeout it would be necessary to define the value outside in the devicetree.

So DC_OK_IRQ have the same limitation according to LDO like DC_OK in HW_POWER_STS?

Stefan

0 Kudos
702 Views
igorpadykov
NXP Employee
NXP Employee

Hi Stefan

yes limitation the same.

Best regards

igor

0 Kudos