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using iMX6 SSI as master

Question asked by Ed Nash on Sep 30, 2014
Latest reply on Oct 1, 2014 by Fabio Estevam

I am trying to use a tlv320dac3100 codec as a slave. MCLK in the codec is not connected, so I need BCLK provided by the processor.

 

So far, I have not been able to see a clock output from AUDMUX port 5. Here's what I have done so far.

 

Thanks in advance for any help.

 

In the SSI to generate a clock that's 44100*32*2 (I2S requires 32 bit words):

 

       /*

        * the target is 11289600 Hz as a good starting point per RM

        * section 61.8.4.2. Because the clk_round_rate() function

        * rounds down, we ask for a slightly higher target to get a closer

        * value. We will end up with a rate of 11294117 HZ

       */

       clk_set_rate(ssi->clk, clk_round_rate(ssi->clk, 11294118));

 

Then in the codec driver I have:

 

     snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_PM, 1);

     snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_2, 0);

     snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_PSR, 0);

 

ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |

                              SND_SOC_DAIFMT_NB_IF |

                              SND_SOC_DAIFMT_CBS_CFS);

 

 

AUDMUX is configured as follows:

 

slave=5

master-2

 

slave = slave - 1;

master = master - 1;

 

ptcr = MXC_AUDMUX_V2_PTCR_TFSDIR |

     MXC_AUDMUX_V2_PTCR_TFSEL(master) |

     MXC_AUDMUX_V2_PTCR_TCLKDIR |

     MXC_AUDMUX_V2_PTCR_TCSEL(master);

     pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(master);

 

mxc_audmux_v2_configure_port(slave, ptcr, pdcr);

 

ptcr = 0;

pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(slave);

mxc_audmux_v2_configure_port(master, ptcr, pdcr);

 

I have the codec set BCLK as input.

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