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Question asked by Adam Szalkowski on Sep 29, 2014
Latest reply on Oct 2, 2014 by Naoum Gitnik

The Vybrid manual claims that during QuadSPI commands IOFx[3:2] are "driven all the time, values taken from QSPI_MCR[ISDnFx]".

I can not find any information on these two bits in the documentation of the QSPIx_MCR register. Where can I find this information.


The other question is how to drive these two pins to HIGH during QuadSPI boot? Are there any undocumented eFuses for this purpose?

Currently, these pins are low during boot and thus the HOLD# pin is active, which leads to no data being transferred.


Best regards,