Mark Butcher

M5223X Edge Port interrupt priorities

Discussion created by Mark Butcher on Sep 13, 2007
Latest reply on Sep 17, 2007 by Oriol Bayo Puxan
Hi All

I am trying to clear up an issue with Edge Ports on M5223X.

The user manual states that the edge port consists of IRQ line 1..7, but there are 2 edge port control registers and all together IRQ1..15. I am assuming that there are this really 15 edge ports as defined.

It is stated that the edge port have a fixed mid point priority (0x8) for IRQ1..7, where the user can still define an interrupt level (1..7). No two interrupt sources should have the same level/prioity.
This means that if IRQ1..IRQ7 are used, each must have a differnet priority level from 1..7 and the one with level 7 will in effect become a NMI (can not be masked).

Has this been understood correctly?

The thing which is giving a bit of confusion is to do with the IRQ8..15 interrupts.
Are these also assigned a fixed mid pint priority or can the user define any mix of level and priority?
It does in fact seem logical that they are free since the IRQ1..7 would have already used up all the mid-level priority/level combinations.

But can any one give a definite answer??

Regards

Mark Butcher



Outcomes