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How to fix DDR bus width with i.MX6DL-Sabre board

Question asked by torus1000 on Sep 17, 2014
Latest reply on Sep 17, 2014 by igorpadykov

Hi,
Now I try to check i.MX6S performance with i.MX6DL-Sabre board.
I think big difference between i.MX6S and i.MX6DL are core number and DDR bus width.
I only know how to disables one of dual core.

 

Does anyone know how to fix DDR bus width to x32?

Is it available to set 01 to MDCTL[DSIZ] after kernel bootup?
(Running change is OK for it?)

 

Thanks

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