i.MX6 enfc_clk and CCM_CCGR2 CG7.

[satoshishimoda]

Hi community,

Our partner have a question about i.MX6SDL Linxu BSP.

Please see static struct clk enfc_clk in arch/arm/mach-mx6/clock.c in L3.0.35_4.1.0_ER.

static struct clk enfc_clk = {

__INIT_CLK_DEBUG(enfc_clk)

  .id = 0,

  .parent = &pll2_pfd_352M,

  .enable_reg = MXC_CCM_CCGR2,

  .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,

  .enable = _clk_enable,

  .disable = _clk_disable,

  .set_rate = _clk_enfc_set_rate,

  .get_rate = _clk_enfc_get_rate,

  .round_rate = _clk_enfc_round_rate,

  .set_parent = _clk_enfc_set_parent,

};

According to this code, CCM_CCGR2 and CG7 seem enfc clock controle register and field.

On the other hand, these are seem iomux_ipt_clk_io_enable in IMX6SDLRM Rev.1.

Which is correct?

Or Freescale set CCGR2 CG7 for encf even though these are not for enfc originally since there is some reason?

Best Regards,

Satoshi Shimoda

[igorpadykov · Accepted solution]

Hi Satoshi

enfc_clk is root clock for ipt_clk_io IOMUX according to p.799

sect.18.4 System Clocks IMX6SDLRM

there is also struct clk gpmi_nand_clk with

gating CCM_CCGR4 options

Best regards

igor

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[satoshishimoda]

Hi igor,

Thank you for your reply.

> enfc_clk is root clock for ipt_clk_io IOMUX according to p.799

> sect.18.4 System Clocks IMX6SDLRM

OK, I understood.

According to your reply, user cannot stop enfc_clk directory, so the source code control the ipt_clk_io gating instead of enfc_clk.

Is this correct?

> there is also struct clk gpmi_nand_clk with

> gating CCM_CCGR4 options

I checked the code of struct clk gpmi_nand_clk, and I understood the parent clock of it is "enfc_clk".

In this case, if user stops ipt_clk_io, does gpmi_nand_clk stop also?

Best Regards,

Satoshi Shimoda

[igorpadykov]

Hi Satoshi

yes, correct code gates the ipt_clk_io,

gpmi_nand_clk is not stopped by gating the ipt_clk_io.

gpmi_nand_clk have own independent gates in CCM_CCGR4.

Best regards

igor