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lcdif_pix_clk_enable

Question asked by Rajkumar Madhani on Sep 5, 2014
Latest reply on Oct 3, 2014 by Tyler Sheffield

In my u-boot code  working on LCD . lcdif_pix_clk is not running .

these are clock controlling registers.

 

Anything  am i missing in clock configuration  ?

 

     /* LCDIF AXI clk from PFD_400M, set to 396/2 = 198MHz */
    reg = readl(CCM_BASE_ADDR + CLKCTL_CSCDR3);
    reg &= ~0x7C000;
    reg |= (0x1 << 16) | (1 << 14);     //reg = 0x00014000
    writel(reg, CCM_BASE_ADDR + CLKCTL_CSCDR3);

 

    /* LCDIF AXI clk enable */
    reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR3);
    reg |= 0x00C0;
    writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR3);

 

    /* LCDIF PIX clk from PFD_540M, set to 540/4/5 = 27MHz */
    reg = readl(CCM_BASE_ADDR + CLKCTL_CSCDR2);
    reg &= ~0x0FFF;
    reg |= (0x5 << 6) | (1 << 5);
    writel(reg, CCM_BASE_ADDR + CLKCTL_CSCDR2);

 

 

    /* POST DIVIDET for lcdif pix clk */
    reg = readl(CCM_BASE_ADDR + CLKCTL_CSCMR1);
    reg &= ~0x00700000;
    reg |= (0x5 << 20);
    writel(reg, CCM_BASE_ADDR + CLKCTL_CSCMR1);

 

    /* LCDIF PIX clk enable */
    reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR3);
    reg |= 0x03C0;
    writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR3);

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