AnsweredAssumed Answered

I'm using the TWR-VF65GS10_a5 board with MQX Rev. 4.0.2 and cannot get the DDR3 RAM to initialize properly

Question asked by Joe Stroupe on Sep 4, 2014
Latest reply on Sep 29, 2014 by jiri-b36968

I'm using IAR v6.7 tools and JLink probe. The DDR3 setup macro I'm using fails when trying to read a register to verify that PLL lock is accomplished:





    __var tmp;

    // Use 396MHz CA5, 396MHz DDR, 132MHz CM4, and 66MHz bus

    __writeMemory32(0x00010005, 0x4006b000, "Memory"); // CCM_CCR: FIRC_EN=1 and OSCNT=5

    __writeMemory32(0x0003FF24, 0x4006b008, "Memory"); // CCM_CCSR: PLL1 uses PLL1_PFD3, enable all PLL1 and PLL2, select Fast Clock, and sys_clock_sel use PLL1

    __writeMemory32(0x00000850, 0x4006b00c, "Memory"); // CCM_CACRR: ARM_DIV=0 (div by 1), BUS_DIV=2 (div by 3), ipg_div value is 1 (div by 2), PLL4 value is 1 (div 4)



    __writeMemory32(0x00002001, 0x40050030, "Memory"); // Anadig_PLL_528_CTRL

    __writeMemory32(0x00002001, 0x40050270, "Memory"); // Anadig_PLL_SYS_CTRL

    __writeMemory32(0x00002031, 0x40050070, "Memory"); // Anadig_PLL_AUDIO_CTRL: PLL4

    __writeMemory32(0x00002001, 0x400500e0, "Memory"); // Anadig_PLL_ENET_CTRL: PLL5

    __writeMemory32(0x00002028, 0x400500a0, "Memory"); // Anadig_PLL_VIDEO_CTRL: PLL6



    __message "wait to pll lock";

    while (~__readMemory32(0x400502c0, "Memory") & 0x7c)





This same macro works on another identical TWR setup with identical Vybrid, etc. All jumper settings are identical.


I have to believe that for some reason this board is seeing a conflict somewhere. I tried to set the boot jumpers on J22 to prevent other code from running - 1-2 and 3-4 jumpers open, but that did not help. What should jumpers 5-6, 7-8, and 9-10 be set to in order to prevent other code from running?


I'm certain that the quad-spi flash has some code flashed into it, because that code tries to execute sometimes when I attempt to debug in DDR mode.


I have no problems running code from internal RAM.


Do I need to erase the quad-spi flash to make sure it isn't causing my DDR3 init problems?


What else might be preventing DDR3 init from succeeding?