I'm using the TWR-VF65GS10_a5 board with MQX Rev. 4.0.2 and cannot get the DDR3 RAM to initialize properly

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I'm using the TWR-VF65GS10_a5 board with MQX Rev. 4.0.2 and cannot get the DDR3 RAM to initialize properly

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joestroupe
Contributor I

I'm using IAR v6.7 tools and JLink probe. The DDR3 setup macro I'm using fails when trying to read a register to verify that PLL lock is accomplished:

.....

clock_init()

{

    __var tmp;

    // Use 396MHz CA5, 396MHz DDR, 132MHz CM4, and 66MHz bus

    __writeMemory32(0x00010005, 0x4006b000, "Memory"); // CCM_CCR: FIRC_EN=1 and OSCNT=5

    __writeMemory32(0x0003FF24, 0x4006b008, "Memory"); // CCM_CCSR: PLL1 uses PLL1_PFD3, enable all PLL1 and PLL2, select Fast Clock, and sys_clock_sel use PLL1

    __writeMemory32(0x00000850, 0x4006b00c, "Memory"); // CCM_CACRR: ARM_DIV=0 (div by 1), BUS_DIV=2 (div by 3), ipg_div value is 1 (div by 2), PLL4 value is 1 (div 4)

   

   

    __writeMemory32(0x00002001, 0x40050030, "Memory"); // Anadig_PLL_528_CTRL

    __writeMemory32(0x00002001, 0x40050270, "Memory"); // Anadig_PLL_SYS_CTRL

    __writeMemory32(0x00002031, 0x40050070, "Memory"); // Anadig_PLL_AUDIO_CTRL: PLL4

    __writeMemory32(0x00002001, 0x400500e0, "Memory"); // Anadig_PLL_ENET_CTRL: PLL5

    __writeMemory32(0x00002028, 0x400500a0, "Memory"); // Anadig_PLL_VIDEO_CTRL: PLL6

    //while (~Anadig_PLL_LOCK & (Anadig_PLL_LOCK_PLL_ENET_LOCK_MASK | Anadig_PLL_LOCK_PLL_VIDEO_LOCK_MASK | Anadig_PLL_LOCK_PLL_AUDIO_LOCK_MASK | Anadig_PLL_LOCK_PLL_528_LOCK_MASK | Anadig_PLL_LOCK_PLL_528_SYS_LOCK_MASK));

    __message "wait to pll lock";

    while (~__readMemory32(0x400502c0, "Memory") & 0x7c)

    {

    }

......

This same macro works on another identical TWR setup with identical Vybrid, etc. All jumper settings are identical.

I have to believe that for some reason this board is seeing a conflict somewhere. I tried to set the boot jumpers on J22 to prevent other code from running - 1-2 and 3-4 jumpers open, but that did not help. What should jumpers 5-6, 7-8, and 9-10 be set to in order to prevent other code from running?

I'm certain that the quad-spi flash has some code flashed into it, because that code tries to execute sometimes when I attempt to debug in DDR mode.

I have no problems running code from internal RAM.

Do I need to erase the quad-spi flash to make sure it isn't causing my DDR3 init problems?

What else might be preventing DDR3 init from succeeding?

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This an automatic process.

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CommunityBot
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This an automatic process.

We are marking this post as solved, due to the either low activity or any reply marked as correct.

If you have additional questions, please create a new post and reference to this closed post.

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timesyssupport
Senior Contributor II

Hello Joe,

Can you compare your clock init code to the clock init code in either MQX (mqx/source/bsp/twrvf65gs10_m4/init_hw.c) or U-Boot (link to relevant source file below)? We have not seen this issue using either MQX or U-Boot.

https://linuxlink.timesys.com/git?repo=u-boot.git&view=tree&path=board/freescale/vf610twr/vf610twr.c...

Thanks,


Timesys Support

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jiri-b36968
NXP Employee
NXP Employee

Hi Joe,

well, it really looks like that it is hold on that line. It can mean that jLink is not able to read from this address or maybe waiting too long (not sure how it is implemented in jLink). This can mean also that one or more PLLs cannot lock. Please try to use attached mac file (MQX 4.1.1) it read lock bit from PLL CTRL registers. You can also check if XTAL oscillating on TWR module which does not work.

/Jiri

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joestroupe
Contributor I

It turns out that the issue I was having related to Eclipse Olympus - its IAR plugin was not executing the IAR DDR3 RAM init script correctly. After playing with the reset parameter (changing from hardware reset to software reset) I got the init script to run and everything works now. I HATE ECLIPSE!!!!

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jiri-b36968
NXP Employee
NXP Employee

Hi Joe,

Nice to hear that it works for you. Eclipse is not bad. I personally like it (have not tried IAR one, working in DS-5). It simply has some advantages and some disadvantages.

/Jiri

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naoumgitnik
Senior Contributor V

Dear Joe,

Before we proceed further, according to the sticker by the battery holder, what SCH-27442 revision are you using, please? And what Vybrid chip version is used - 1N02G, etc.?

Please, provide this information for the hardware that does and does not work properly.


timesyssupport, maybe you may already comment something only based on the code fragment provided, please?


Thanks, Naoum Gitnik.

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joestroupe
Contributor I

Hi Naoum,

On the board that works fine for DDR, the SCH-27442 rev is “G”.

On the board that does not work for DDR, the rev is “G3”.

Both boards’ Vybrid chips are 1N02G.

Thanks,

Joe Stroupe

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naoumgitnik
Senior Contributor V

Thanks Joe.

Both G and G3 should behave the same way from the SW point of view.

Let's see how the SW people comment it, which might take a few days  (the team is located globally).

Regards, Naoum Gitnik.

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karina_valencia
NXP Apps Support
NXP Apps Support

timesyssupport can you help to review this case?

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joestroupe
Contributor I

Here’s the debug console log – do you see anything suspicious here?

9/5/14 9:25:16 AM C-SPY Server 6.6.5.2892, built on 12:21:20 Oct 28 2013

9/5/14 9:25:16 AM Initializing base services

9/5/14 9:25:16 AM Processor module: C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.7\arm\bin\armproc.dll

9/5/14 9:25:16 AM Debugger driver: C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.7\arm\bin\armjlink.dll

9/5/14 9:25:16 AM Configuring debugger driver:

9/5/14 9:25:16 AM --backend

9/5/14 9:25:16 AM -B

9/5/14 9:25:16 AM --endian

9/5/14 9:25:16 AM little

9/5/14 9:25:16 AM --cpu=Cortex-A5

9/5/14 9:25:16 AM --fpu=VFPv4

9/5/14 9:25:16 AM -p

9/5/14 9:25:16 AM C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.7\arm\config\debugger\Freescale\VF6xx_A5.ddf

9/5/14 9:25:16 AM --drv_verify_download

9/5/14 9:25:16 AM --semihosting

9/5/14 9:25:16 AM --device=VF6xx_A5

9/5/14 9:25:16 AM --drv_communication=USB0

9/5/14 9:25:16 AM --jlink_speed=auto

9/5/14 9:25:16 AM --jlink_initial_speed=32

9/5/14 9:25:16 AM --jlink_reset_strategy=1000,0

9/5/14 9:25:16 AM --jlink_interface=JTAG

9/5/14 9:25:16 AM --drv_swo_clock_setup=72000000,0,2000000

9/5/14 9:25:18 AM Initializing driver services

9/5/14 9:25:18 AM Loading plugin: C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.7\common\plugins\ServiceCodeCoveragePlugin\ServiceCodeCoveragePlugin.dll

9/5/14 9:25:18 AM Available user breakpoint categories:

9/5/14 9:25:18 AM EMUL_CODE

9/5/14 9:25:18 AM EMUL_DATA

9/5/14 9:25:18 AM STD_LOG2

9/5/14 9:25:18 AM EMUL_TRACE_START

9/5/14 9:25:18 AM EMUL_TRACE_STOP

9/5/14 9:25:18 AM EMUL_TRACE_FILTER

9/5/14 9:25:18 AM Available user breakpoint descriptors:

9/5/14 9:25:18 AM

9/5/14 9:25:18 AM Debug session opened successfully

9/5/14 9:25:18 AM Initializing flash loader manager using: C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.7\arm\config\flashloader

9/5/14 9:25:18 AM Skipping flash loading as the specified configuration file is a folder

9/5/14 9:25:18 AM Loaded macro file: F:\TestAssets\Smyths_Vybrid-selected\Smyths\SmythsExport\SmythsExport\MQX\twrvf65gs10_ddr.mac

9/5/14 9:25:18 AM Loading module: F:\TestAssets\Smyths_Vybrid-selected\Smyths\SmythsExport\SmythsExport\Altia\DDR_Debug\Altia.out

9/5/14 9:25:18 AM Module loading options:

callUserMacros: true

onlyPrefixNotification: false

resetAfterLoad: true

suppressDownload: false

9/5/14 9:25:21 AM Warning: Out of sync , resynchronizing...

9/5/14 9:25:22 AM J-Link communication resynchronized

9/5/14 9:25:22 AM JLINK command: ProjectFile = F:\TestAssets\Smyths_Vybrid-selected\Smyths\SmythsExport\SmythsExport\Altia\settings\Altia_Eclipse Debug.jlink, return = 0

9/5/14 9:25:22 AM Device "VF6XX_A5" selected (0 KB flash, 0 KB RAM).

9/5/14 9:25:22 AM DLL version: V4.78e, compiled Oct 25 2013 11:30:56

9/5/14 9:25:22 AM Firmware: J-Link ARM V6 compiled Jun 20 2012 19:43:26

9/5/14 9:25:22 AM JTAG speed is initially set to: 32 kHz

9/5/14 9:25:22 AM TotalIRLen = 4, IRPrint = 0x01

9/5/14 9:25:22 AM TotalIRLen = 4, IRPrint = 0x01

9/5/14 9:25:22 AM ARM AP[0]: 0x04770001, AHB-AP

9/5/14 9:25:22 AM ARM AP[1]: 0x04770002, APB-AP

9/5/14 9:25:22 AM ARM AP[2]: 0x04760000, JTAG-AP

9/5/14 9:25:22 AM ARM AP[3]: 0x04770001, AHB-AP

9/5/14 9:25:23 AM Found Cortex-A5 r0p1

9/5/14 9:25:23 AM 3 code breakpoints, 2 data breakpoints

9/5/14 9:25:23 AM Data endian: little

9/5/14 9:25:23 AM Main ID register: 0x410FC051

9/5/14 9:25:23 AM Cache Type register: 0x83338003

9/5/14 9:25:23 AM System control register:

9/5/14 9:25:23 AM Instruction endian: little

9/5/14 9:25:23 AM Level-1 instruction cache enabled

9/5/14 9:25:23 AM Level-1 data cache disabled

9/5/14 9:25:23 AM MMU disabled

9/5/14 9:25:23 AM Branch prediction supported

9/5/14 9:25:28 AM Hardware reset with strategy 0 was performed

9/5/14 9:25:28 AM Initial reset was performed

9/5/14 9:25:28 AM Found 1 JTAG device, Total IRLen = 4:

9/5/14 9:25:28 AM #0 Id: 0x4BA00477, IRLen: 4, IRPrint: 0x1 CoreSight JTAG-DP

9/5/14 9:25:30 AM wait to pll lock

9/5/14 9:25:30 AM F:\TestAssets\Smyths_Vybrid-selected\Smyths\SmythsExport\SmythsExport\MQX\twrvf65gs10_ddr.mac(376,27): Error: Operation error.

9/5/14 9:25:30 AM Error while calling macro execUserPreload

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jiri-b36968
NXP Employee
NXP Employee

Hi Joe,

I presume that you have not blown fuses to boot from selected source. To be sure that no other code run after reset, please set J22 to bot from SD card (default 10110) and remove it.

It seems to me that script code does not set correctly SDRAM/DDR3 interface so write operation fails. I presume that you are using sample code script for jLink. Please modify line:

reg32_write(0x400ae268, 0x00000000);    // pad_zq: _early_cmp_en_timer, _mode, _hw_for, _cmp_out_smp

to

reg32_write(0x400ae268, 0x682C0000);     //correct setting for silicon rev1.1 and higher

or

reg32_write(0x400ae268, 0x682C4000);    //correct setting for silicon rev1.1 and higher with immediate calibration

/Jiri

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joestroupe
Contributor I

Hi Jiri,

I do have J22 set exactly as you say – to boot from SD card, and I have SD card removed.

As for the script to set up DDR, I’m not sure where your script comes from. I am using this script below, along with a j-link probe (though the probe is pretty old, and I have a new jlink-plus arriving tomorrow:

This is the entire script I am using:

reg32_write(addr, val)

{

__writeMemory32(val, addr, "Memory");

}

ddr_iomuxc()

{

// __var DDR_IOMUX, DDR_IOMUX1;

// __var p;

// iomux

// DDR_IOMUX = (4 << 6); //0x100;

// DDR_IOMUX1 = (2 << 16) || (4 << 6); //0x20100;

// for (p = 0x4004821c; p <= 0x400482e0; p += 4) {

// if (p == 0x40048274 || p == 0x400482c4 || p == 0x400482c8) {

// __writeMemory32(0x20100, p, "Memory");

// }

// else {

// __writeMemory32(0x100, p, "Memory");

// }

// }

__writeMemory32(0x100, 0x4004821c, "Memory");

__writeMemory32(0x100, 0x40048220, "Memory");

__writeMemory32(0x100, 0x40048224, "Memory");

__writeMemory32(0x100, 0x40048228, "Memory");

__writeMemory32(0x100, 0x4004822c, "Memory");

__writeMemory32(0x100, 0x40048230, "Memory");

__writeMemory32(0x100, 0x40048234, "Memory");

__writeMemory32(0x100, 0x40048238, "Memory");

__writeMemory32(0x100, 0x4004823c, "Memory");

__writeMemory32(0x100, 0x40048240, "Memory");

__writeMemory32(0x100, 0x40048244, "Memory");

__writeMemory32(0x100, 0x40048248, "Memory");

__writeMemory32(0x100, 0x4004824c, "Memory");

__writeMemory32(0x100, 0x40048250, "Memory");

__writeMemory32(0x100, 0x40048254, "Memory");

__writeMemory32(0x100, 0x40048258, "Memory");

__writeMemory32(0x100, 0x4004825c, "Memory");

__writeMemory32(0x100, 0x40048260, "Memory"); // BA 0

__writeMemory32(0x100, 0x40048264, "Memory"); // BA 1

__writeMemory32(0x100, 0x40048268, "Memory"); // BA 0

__writeMemory32(0x100, 0x4004826c, "Memory"); // CAS b

__writeMemory32(0x100, 0x40048270, "Memory"); // CKE 0

__writeMemory32(0x20100, 0x40048274, "Memory"); // CLK 0

__writeMemory32(0x100, 0x40048278, "Memory");

__writeMemory32(0x100, 0x4004827c, "Memory");

__writeMemory32(0x100, 0x40048280, "Memory");

__writeMemory32(0x100, 0x40048284, "Memory");

__writeMemory32(0x100, 0x40048288, "Memory");

__writeMemory32(0x100, 0x4004828c, "Memory");

__writeMemory32(0x100, 0x40048290, "Memory");

__writeMemory32(0x100, 0x40048294, "Memory");

__writeMemory32(0x100, 0x40048298, "Memory");

__writeMemory32(0x100, 0x4004829c, "Memory");

__writeMemory32(0x100, 0x400482a0, "Memory");

__writeMemory32(0x100, 0x400482a4, "Memory");

__writeMemory32(0x100, 0x400482a8, "Memory");

__writeMemory32(0x100, 0x400482ac, "Memory");

__writeMemory32(0x100, 0x400482b0, "Memory");

__writeMemory32(0x100, 0x400482b4, "Memory");

__writeMemory32(0x100, 0x400482b8, "Memory");

__writeMemory32(0x100, 0x400482bc, "Memory"); // DQM 1

__writeMemory32(0x100, 0x400482c0, "Memory"); // DQM 0

__writeMemory32(0x20100, 0x400482c4, "Memory"); // DQS 1

__writeMemory32(0x20100, 0x400482c8, "Memory"); // DQS 0

__writeMemory32(0x100, 0x400482cc, "Memory"); // RAS

__writeMemory32(0x100, 0x400482d0, "Memory"); // WE

__writeMemory32(0x100, 0x400482d4, "Memory"); // ODT 0

__writeMemory32(0x100, 0x400482d8, "Memory"); // ODT 1

__writeMemory32(0x100, 0x400482dc, "Memory");

__writeMemory32(0x100, 0x400482e0, "Memory");

}

ddr_phy_init2()

{

__var PHY_DQ_TIMING;

__var PHY_DQS_TIMING;

__var PHY_CTRL;

__var PHY_MASTER_CTRL;

__var PHY_SLAVE_CTRL;

PHY_DQ_TIMING = 0x00002613;

PHY_DQS_TIMING = 0x00002615;

PHY_CTRL = 0x01210080;

// PHY_MASTER_CTRL = 0x0000002a;

// PHY_SLAVE_CTRL = 0x00002000;

PHY_MASTER_CTRL = 0x0001012a;

PHY_SLAVE_CTRL = 0x00012020;

// phy_dq_timing_reg freq set 0

reg32_write(0x400ae400, PHY_DQ_TIMING);

reg32_write(0x400ae440, PHY_DQ_TIMING);

reg32_write(0x400ae480, PHY_DQ_TIMING);

reg32_write(0x400ae4c0, PHY_DQ_TIMING);

// phy_dqs_timing_reg freq set 0

reg32_write(0x400ae404, PHY_DQS_TIMING);

reg32_write(0x400ae444, PHY_DQS_TIMING);

reg32_write(0x400ae484, PHY_DQS_TIMING);

reg32_write(0x400ae4c4, PHY_DQS_TIMING);

// phy_gate_lpbk_ctrl_reg freq set 0

reg32_write(0x400ae408, PHY_CTRL); // read delay bit21:19

reg32_write(0x400ae448, PHY_CTRL); // phase_detect_sel bit18:16

reg32_write(0x400ae488, PHY_CTRL); // bit lpbk_ctrl bit12

reg32_write(0x400ae4c8, PHY_CTRL);

// phy_dll_master_ctrl_reg freq set 0

reg32_write(0x400ae40c, PHY_MASTER_CTRL);

reg32_write(0x400ae44c, PHY_MASTER_CTRL);

reg32_write(0x400ae48c, PHY_MASTER_CTRL);

reg32_write(0x400ae4cc, PHY_MASTER_CTRL);

// phy_dll_slave_ctrl_reg freq set 0

reg32_write(0x400ae410, PHY_SLAVE_CTRL);

reg32_write(0x400ae450, PHY_SLAVE_CTRL);

reg32_write(0x400ae490, PHY_SLAVE_CTRL);

reg32_write(0x400ae4d0, PHY_SLAVE_CTRL);

// reg32_write(0x400ae508, 0x00005105);

// reg32_write(0x400ae50c, 0x00005104);

reg32_write(0x400ae4c8, 0x00001105);

}

ddr_init()

{

__var MR, MR1, MR2;

__var i;

// Dram Device Parameters

reg32_write(0x400ae000, 0x00000600); // LPDDR2 or DDR3

reg32_write(0x400ae008, 0x00000020); // TINIT F0

// cold boot - 1ms??? 0x61a80

reg32_write(0x400ae028, 0x0000007c); // reset during power on

// warm boot - 200ns

reg32_write(0x400ae02c, 0x00013880); // 500us - 10ns

reg32_write(0x400ae030, 0x0000050c); // CASLAT_LIN, WRLAT

reg32_write(0x400ae034, 0x15040404); // trc, trrd, tccd, tbst_int_interval

reg32_write(0x400ae038, 0x1406040F); // tfaw, trp, twtr, tras_min

reg32_write(0x400ae040, 0x04040000); // tmrd, trtp

reg32_write(0x400ae044, 0x006db00c); // tras_max, tmod

reg32_write(0x400ae048, 0x00000403); // tckesr, tcke

reg32_write(0x400ae050, 0x01000403); // ap, writeinterp, tckesr_f1, tcke_f1

reg32_write(0x400ae054, 0x06060101); // twr_int, trcd_int, tras_lockout, ccAP

reg32_write(0x400ae058, 0x000b0000); // tdal

reg32_write(0x400ae05c, 0x03000200); // bstlen, tmrr - lpddr2, tdll

reg32_write(0x400ae060, 0x00000006); // addr_mirror, reg_dimm, trp_ab

reg32_write(0x400ae064, 0x00010000); // tref_enable, auto_refresh, arefresh

reg32_write(0x400ae068, 0x0c28002c); // tref, trfc

reg32_write(0x400ae070, 0x00000005); // tref_interval fixed at 5

reg32_write(0x400ae074, 0x00000003); // tpdex_f0

reg32_write(0x400ae078, 0x0000000a); // txpdll

reg32_write(0x400ae07c, 0x00440200); // txsnr, txsr

reg32_write(0x400ae084, 0x00010000); // cke_dly, en_quick_srefresh,

// srefresh_exit_no_refresh,

// pwr, srefresh_exit

reg32_write(0x400ae088, 0x00050500); // cksrx_f0,

// cksre_f0, lowpwr_ref_en

//

// Frequency change

//

reg32_write(0x400ae098, 0x00000100); // freq change...

reg32_write(0x400ae09c, 0x04001002); // PHY_INI: com, sta, freq_ch_dll_off

reg32_write(0x400ae0a4, 0x00000001); // 15.02 - allow dfi_init_start

reg32_write(0x400ae0b4, 0x00000000); // wrmd

reg32_write(0x400ae0b8, 0x00000000); // rmd

reg32_write(0x400ae0bc, 0x00000000); // REF_PER_AUTO_TEMPCHK: LPDDR2 set to 2, else 0

//

// DRAM device Mode registers

//

//#define MR_BL_FIXED8 0x0000 // Fixed 8

//#define MR_BL_4_8_A12 0x0001 // 4 or 8 on A12

//#define MR_BL_FIXED4 0x0002 // Fixed 4

//#define MR_CAS_5 0x0010 // CAS 5

//#define MR_CAS_6 0x0020 // CAS 6

//#define MR_CAS_7 0x0030 // CAS 7

//#define MR_CAS_8 0x0040 // CAS 8

//#define MR_CAS_9 0x0050 // CAS 9

//#define MR_CAS_10 0x0060 // CAS 10

//#define MR_CAS_11 0x0070 // CAS 11

//#define MR_CAS_12 0x0004 // CAS 12

//#define MR_CAS_13 0x0014 // CAS 13

//#define MR_WR_5 0x0200 // Write Recovery 5

//#define MR_WR_6 0x0400 // Write Recovery 6

//#define MR_WR_7 0x0600 // Write Recovery 7

//#define MR_WR_8 0x0800 // Write Recovery 8

//#define MR_WR_10 0x0A00 // Write Recovery 10

//#define MR_WR_12 0x0C00 // Write Recovery 12

//#define MR_WR_14 0x0E00 // Write Recovery 14

//#define MR (MR_BL_FIXED8 | MR_CAS_6 | MR_WR_6)

MR = 0x0420;

//#define MR1_ODS_RZQ_6 0x0000 // drvstrength 40 ohm

//#define MR1_ODS_RZQ_7 0x0002 // drvstrength 34 ohm

//#define MR1_AL_DIS 0x0000

//#define MR1_AL_1 0x0008 // CL - 1

//#define MR1_AL_2 0x0010 // CL - 2

//#define MR1_ODT_DIS 0x0000

//#define MR1_ODT_RZQ_4 0x0004 // RZQ/4 60 ohm

//#define MR1_ODT_RZQ_2 0x0040 // RZQ/2 120 ohm

//#define MR1_ODT_RZQ_6 0x0044 // RZQ/6 40 ohm

//#define MR1_ODT_RZQ_12 0x0200 // RZQ/12 20 ohm

//#define MR1_ODT_RZQ_8 0x0204 // RZQ/8 30 ohm

//#define MR1_WL 0x0080 // Write Leveling

//#define MR1_QOFF 0x0400 // Q off

//#define MR1 (MR1_ODS_RZQ_7 | MR1_AL_DIS | MR1_ODT_RZQ_6)

MR1 = 0x46;

//#define MR2_CWL_5CK 0x0000 // 5ck (tCK >= 2.5 ns)

//#define MR2_CWL_6CK 0x0008 // 6ck (2.5 ns > tCK >= 1.875 ns)

//#define MR2_CWL_7CK 0x0010 // 7ck (1.875 ns > tCK >= 1.5 ns)

//#define MR2_CWL_8CK 0x0018 // 8ck (1.5 ns > tCK >= 1.25 ns)

//#define MR2_CWL_9CK 0x0020 // 9ck (1.25 ns > tCK >= 1.07 ns)

//#define MR2_DODT_DIS 0x0000

//#define MR2_DODT_RZQ_4 0x0200 // RZQ / 4

//#define MR2_DODT_RZQ_2 0x0400 // RZQ / 2

//#define MR2 (MR2_CWL_5CK | MR2_DODT_DIS)

MR2 = 0x07;

reg32_write(0x400ae0c0, ((MR1 << 16) | MR)); // mr0, ddr3 burst of 8 only

// mr1, if freq < 125, dll_dis = 1, rtt = 0

// if freq > 125, dll_dis = 0, rtt = 3

reg32_write(0x400ae0c4, MR2); // mr0_f1_0 & mr2_f0_0

reg32_write(0x400ae0cc, 0x00000000); // mr3 & mrsingle_data

reg32_write(0x400ae0d0, 0x00000000); // mr17, mr16

// ECC

reg32_write(0x400ae0e4, 0x00000000); // ctrl_raw

// ctrl_raw, if DDR3, set 3, else 0

reg32_write(0x400ae0e8, 0x00000000);

//

// ZQ stuff

//

reg32_write(0x400ae108, 0x01000200); // zqcl, zqinit

reg32_write(0x400ae10c, 0x02000040); // zqcs

reg32_write(0x400ae114, 0x00000200); // zq_on_sref_exit, qz_req

reg32_write(0x400ae118, 0x00000040); // ref_per_zq

reg32_write(0x400ae11c, 0x00000000); // zqreset, ddr3 set to 0

reg32_write(0x400ae120, 0x01000000); // zqcs_rotate, no_zq_init, zqreset_f1

//

// DRAM controller misc

//

reg32_write(0x400ae124, 0x0a010300); // arebit, col_diff, row_diff, bank_diff

reg32_write(0x400ae128, 0x0101ffff); // bank_split, addr_cmp_en, cmd/age cnt

reg32_write(0x400ae12c, 0x01010101); // rw same pg, rw same en, pri en, plen

reg32_write(0x400ae130, 0x03030101); // #q_entries_act_dis, (#cmdqueues

// dis_rw_grp_w_bnk_conflict

// w2r_split_en, cs_same_en

reg32_write(0x400ae134, 0x01000101); // cs_map, inhibit_dram_cmd, dis_interleave, swen //by devendra

reg32_write(0x400ae138, 0x0000000c); // qfull, lpddr2_s4, reduc, burst_on_fly

reg32_write(0x400ae13c, 0x01000000); // ctrlupd_req_per aref en, ctrlupd_req

// ctrller busy, in_ord_accept

//

// ODT

//

reg32_write(0x400ae15c, 0x01010000); // odt: wr_map_cs, rd_map_cs, port_data_err_id

reg32_write(0x400ae160, 0x00040000); // todtl_2cmd

// todtl_2cmd = odtl_off = CWL + AL - 2ck

reg32_write(0x400ae164, 0x00000002); // add_odt stuff

reg32_write(0x400ae16c, 0x00020000);

reg32_write(0x400ae170, 0x00000000); // tdqsck_min, max, w2wsmcsdl

reg32_write(0x400ae180, 0x00002819); // wlmrd, wldqsen

// reg32_write(0x400ae1a4, 0x00020200);

// reg32_write(0x400ae1a8, 0x02020000);

// reg32_write(0x400ae1b8, 0x00000202);

// reg32_write(0x400ae1c8, 0x00020200);

// reg32_write(0x400ae1cc, 0x02020000);

reg32_write(0x400ae1a4, 0x00202000);

reg32_write(0x400ae1a8, 0x20200000);

reg32_write(0x400ae1b8, 0x00002020);

reg32_write(0x400ae1c8, 0x00202000);

reg32_write(0x400ae1cc, 0x20200000);

//

// AXI ports

//

reg32_write(0x400ae1d4, 0x00000101); // FIFO type (0-async, 1-2:1, 2-1:2, 3- sync, w_pri, r_pri

reg32_write(0x400ae1d8, 0x01010000); // w_pri, rpri, en

reg32_write(0x400ae1dc, 0x00000000); // fifo_type

reg32_write(0x400ae1e0, 0x02020000);

reg32_write(0x400ae1e4, 0x00000202); // round robin port ordering

reg32_write(0x400ae1e8, 0x01010064);

reg32_write(0x400ae1ec, 0x00010101);

reg32_write(0x400ae1f0, 0x00000064);

//

// TDFI

//

reg32_write(0x400ae1f4, 0x00000000); // dll_rst_adj_dly, dll_rst_delay

reg32_write(0x400ae1f8, 0x00000b00); // phy_rdlat

reg32_write(0x400ae1fc, 0x00000000); // dram_ck_dis

// reg32_write(0x400ae20c, 0x00003cc8); // tdfi_ctrlupd_interval_f0

reg32_write(0x400ae20c, 0); // tdfi_ctrlupd_interval_f0

// #define WRADJ 0x00000500

// #define RDADJ 0x00000006

// #define ADJLAT (WRADJ | RDADJ)

// reg32_write(0x400ae210, ADJLAT); // wrlat, rdlat 15.02

reg32_write(0x400ae210, 0x0506); // wrlat, rdlat 15.02

reg32_write(0x400ae224, 0x00020000); // Phyctl_dl

reg32_write(0x400ae22c, 0x04070303);

// reg32_write(0x400ae220, 0x000012e3); // tdfi_ctrlupd_interval_f1

reg32_write(0x400ae220, 0); // tdfi_ctrlupd_interval_f1

// leveling

// reg32_write(0x400ae228, 0x80000301); // phy_wrlv: resplat, load, dll, en

// reg32_write(0x400ae230, 0x0000000a); // phy_rdlv_ww

// reg32_write(0x400ae234, 0x00000000); // phy_wrlv_resp

// reg32_write(0x400ae23c, 0x0010ffff); // rdlv_gat_mxdl, rdlv_mxdl

// reg32_write(0x400ae240, 0x16070303); // phy_rdlvl: _res, _load, _dll, _en

// reg32_write(0x400ae244, 0x0000000f); // phy_rdlv_rr

// reg32_write(0x400ae248, 0x00000000); // phy_rdlvl_resp

// reg32_write(0x400ae24c, 0x00000000); // rdlv_resp_msk

// reg32_write(0x400ae250, 0x00000000); // rdlvl: _en, gateresp_msk

// reg32_write(0x400ae254, 0x00000000); // rdlvl: gtchkens, gateen

// reg32_write(0x400ae258, 0x00000000); // phy_rdlvlmax

// reg32_write(0x400ae25c, 0x00000204); // rdlv: gatdq_zero_cnt, dqzero_cnt

// reg32_write(0x400ae260, 0x00000000); // rdlv: _gtrefint, _refint

// reg32_write(0x400ae264, 0x00000000); // en_1t_tmg

// reg32_write(0x400ae268, 0x00000000); // pad_zq: earlycmp_en_timer, _mode, hwfor, cmpout_smp

reg32_write(0x400ae268, 0x68200000); // pad_zq: earlycmp_en_timer, _mode, hwfor, cmpout_smp

reg32_write(0x400ae26c, 0x00000202); // pad: ibe1, ibe0, padibe: _sel1, _sel0,

// axi_awcache, axi_cobuf, pad_odt: bate0, byte1

reg32_write(0x400ae278, 0x00000006); // twr

reg32_write(0x400ae27c, 0x00000006); // todth

__delay(100);

ddr_phy_init2();

reg32_write(0x400ae148, 0x1fffffff);

reg32_write(0x400ae000, 0x00000601); // LPDDR2 or DDR3, start

// i = 5000;

// while (i--);

// //ddr_leveling2();

// i = 1000;

// while(i--);

__delay(100);

}

clock_init()

{

__var tmp;

// Use 396MHz CA5, 396MHz DDR, 132MHz CM4, and 66MHz bus

__writeMemory32(0x00010005, 0x4006b000, "Memory"); // CCM_CCR: FIRC_EN=1 and OSCNT=5

__writeMemory32(0x0003FF24, 0x4006b008, "Memory"); // CCM_CCSR: PLL1 uses PLL1_PFD3, enable all PLL1 and PLL2, select Fast Clock, and sys_clock_sel use PLL1

__writeMemory32(0x00000850, 0x4006b00c, "Memory"); // CCM_CACRR: ARM_DIV=0 (div by 1), BUS_DIV=2 (div by 3), ipg_div value is 1 (div by 2), PLL4 value is 1 (div 4)

__writeMemory32(0x00002001, 0x40050030, "Memory"); // Anadig_PLL_528_CTRL

__writeMemory32(0x00002001, 0x40050270, "Memory"); // Anadig_PLL_SYS_CTRL

__writeMemory32(0x00002031, 0x40050070, "Memory"); // Anadig_PLL_AUDIO_CTRL: PLL4

__writeMemory32(0x00002001, 0x400500e0, "Memory"); // Anadig_PLL_ENET_CTRL: PLL5

__writeMemory32(0x00002028, 0x400500a0, "Memory"); // Anadig_PLL_VIDEO_CTRL: PLL6

//while (~Anadig_PLL_LOCK & (Anadig_PLL_LOCK_PLL_ENET_LOCK_MASK | Anadig_PLL_LOCK_PLL_VIDEO_LOCK_MASK | Anadig_PLL_LOCK_PLL_AUDIO_LOCK_MASK | Anadig_PLL_LOCK_PLL_528_LOCK_MASK | Anadig_PLL_LOCK_PLL_528_SYS_LOCK_MASK));

__message "wait to pll lock";

while (~__readMemory32(0x400502c0, "Memory") & 0x7c)

{

}

// enable all clock from CCM

__writeMemory32(0xffffffff, 0x4006b040, "Memory"); // CCM_CCGR0 = 0xffffffff

__writeMemory32(0xffffffff, 0x4006b044, "Memory"); // CCM_CCGR1 = 0xffffffff

__writeMemory32(0xffffffff, 0x4006b048, "Memory"); // CCM_CCGR2 = 0xffffffff

__writeMemory32(0xffffffff, 0x4006b04c, "Memory"); // CCM_CCGR3 = 0xffffffff

__writeMemory32(0xffffffff, 0x4006b050, "Memory"); // CCM_CCGR4 = 0xffffffff

__writeMemory32(0xffffffff, 0x4006b054, "Memory"); // CCM_CCGR5 = 0xffffffff

__writeMemory32(0xffffffff, 0x4006b058, "Memory"); // CCM_CCGR6 = 0xffffffff

__writeMemory32(0xffffffff, 0x4006b05c, "Memory"); // CCM_CCGR7 = 0xffffffff

__writeMemory32(0x3fffffff, 0x4006b060, "Memory"); // CCM_CCGR8 = 0x3fffffff

__writeMemory32(0xffffffff, 0x4006b064, "Memory"); // CCM_CCGR9 = 0xffffffff

__writeMemory32(0xffffffff, 0x4006b068, "Memory"); // CCM_CCGR10 = 0xffffffff

__writeMemory32(0xffffffff, 0x4006b06c, "Memory"); // CCM_CCGR11 = 0xffffffff

}

execUserPreload()

{

// __hwReset(0);

clock_init();

ddr_iomuxc();

__delay(100);

ddr_init();

}

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1,977 Views
jiri-b36968
NXP Employee
NXP Employee

Hi Joe,

great. It looks like the script from sample code:Please modify line:

reg32_write(0x400ae268, 0x68200000);    // pad_zq: _early_cmp_en_timer, _mode, _hw_for, _cmp_out_smp

to

reg32_write(0x400ae268, 0x682C0000);     //correct setting for silicon rev1.1 and higher

or

reg32_write(0x400ae268, 0x682C4000);    //correct setting for silicon rev1.1 and higher with immediate calibration

/Jiri

1,977 Views
joestroupe
Contributor I

So – I am getting the script error, “twrvf65gs10_ddr.mac(376,27): Error: Operation error.” On the __readMemory32(0x400502c0, "Memory") statement in the clock_init() function.

I even tried removing the “while” statement and the AND operation and just had a simple, single read operation (just to be sure the failure was not syntax-related), but the script still fails on that read.

It’s almost as if the external DDR RAM is dead (not powered-up?). But, why would the read operation fail, but not the preceding write operations? Perhaps the write operations are blind (don’t care about success), but read does care?

Is there a software command that needs to be issued to power-up the DDR on this board? Or is there some other command needed in the code before this read operation is performed?

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1,977 Views
joestroupe
Contributor I

Hi Jiri,

I will make that change – I see now where it is in my script.

However, I don’t think my script is even reaching that point before it fails – I am getting a failure in the clock_init() function which runs before the code you asked me to change, at this line below in red, with this error:

9/8/14 9:09:40 AM wait to pll lock

9/8/14 9:09:41 AM F:\TestAssets\Smiths_Vybrid-selected\Smiths\SmithsExport\SmithsExport\MQX\twrvf65gs10_ddr.mac(376,27): Error: Operation error.

9/8/14 9:09:41 AM Error while calling macro execUserPreload

clock_init()

{

__var tmp;

// Use 396MHz CA5, 396MHz DDR, 132MHz CM4, and 66MHz bus

__writeMemory32(0x00010005, 0x4006b000, "Memory"); // CCM_CCR: FIRC_EN=1 and OSCNT=5

__writeMemory32(0x0003FF24, 0x4006b008, "Memory"); // CCM_CCSR: PLL1 uses PLL1_PFD3, enable all PLL1 and PLL2, select Fast Clock, and sys_clock_sel use PLL1

__writeMemory32(0x00000850, 0x4006b00c, "Memory"); // CCM_CACRR: ARM_DIV=0 (div by 1), BUS_DIV=2 (div by 3), ipg_div value is 1 (div by 2), PLL4 value is 1 (div 4)

__writeMemory32(0x00002001, 0x40050030, "Memory"); // Anadig_PLL_528_CTRL

__writeMemory32(0x00002001, 0x40050270, "Memory"); // Anadig_PLL_SYS_CTRL

__writeMemory32(0x00002031, 0x40050070, "Memory"); // Anadig_PLL_AUDIO_CTRL: PLL4

__writeMemory32(0x00002001, 0x400500e0, "Memory"); // Anadig_PLL_ENET_CTRL: PLL5

__writeMemory32(0x00002028, 0x400500a0, "Memory"); // Anadig_PLL_VIDEO_CTRL: PLL6

//while (~Anadig_PLL_LOCK & (Anadig_PLL_LOCK_PLL_ENET_LOCK_MASK | Anadig_PLL_LOCK_PLL_VIDEO_LOCK_MASK | Anadig_PLL_LOCK_PLL_AUDIO_LOCK_MASK | Anadig_PLL_LOCK_PLL_528_LOCK_MASK | Anadig_PLL_LOCK_PLL_528_SYS_LOCK_MASK));

__message "wait to pll lock";

while (~__readMemory32(0x400502c0, "Memory") & 0x7c)

{

}

// enable all clock from CCM

__writeMemory32(0xffffffff, 0x4006b040, "Memory"); // CCM_CCGR0 = 0xffffffff

__writeMemory32(0xffffffff, 0x4006b044, "Memory"); // CCM_CCGR1 = 0xffffffff

__writeMemory32(0xffffffff, 0x4006b048, "Memory"); // CCM_CCGR2 = 0xffffffff

__writeMemory32(0xffffffff, 0x4006b04c, "Memory"); // CCM_CCGR3 = 0xffffffff

__writeMemory32(0xffffffff, 0x4006b050, "Memory"); // CCM_CCGR4 = 0xffffffff

__writeMemory32(0xffffffff, 0x4006b054, "Memory"); // CCM_CCGR5 = 0xffffffff

__writeMemory32(0xffffffff, 0x4006b058, "Memory"); // CCM_CCGR6 = 0xffffffff

__writeMemory32(0xffffffff, 0x4006b05c, "Memory"); // CCM_CCGR7 = 0xffffffff

__writeMemory32(0x3fffffff, 0x4006b060, "Memory"); // CCM_CCGR8 = 0x3fffffff

__writeMemory32(0xffffffff, 0x4006b064, "Memory"); // CCM_CCGR9 = 0xffffffff

__writeMemory32(0xffffffff, 0x4006b068, "Memory"); // CCM_CCGR10 = 0xffffffff

__writeMemory32(0xffffffff, 0x4006b06c, "Memory"); // CCM_CCGR11 = 0xffffffff

}

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