AnsweredAssumed Answered

User Guide Clarification: Cortex-M4F Interrupt Priorities

Question asked by Kenny Koller on Sep 3, 2014
Latest reply on Sep 10, 2014 by Martin Latal

Hi,

 

In revision 12 of the user guide 3.9.3.4 it says the following:

 

On Cortex-M4 and Cortex-A5 core based platforms, the MQX interrupt processing is designed this way. Kinetis K MCUs support 16 hardware interrupt priority levels. Internally MQX maps even levels (0, 2, 4, .., 14) for MQX applications while odd levels (1, 3, .., 15) are used internally. MQX application interrupt levels are 0 to 7, the mapping from MQX application levels 0 to 7 to hardware priority levels (0, 2 to 14) is implemented in the _bsp_int_init() function.

 

I understand the 16 priority levels for the ISRs. This is independent of MQX. But it then states that maps even levels to MQX applications and that odd levels are used internally. What does this mean? Is this saying that interrupts used by the MQX framework or add-ons use odd and that any that I define should be even?

 

Why is 0x60 suspiciously absent from the table? All the evens between 0x00 and 0xF0 are there except 0x60. Wondering if this is a typo.

 

Thanks,

 

Kenny

Outcomes