I meet a trouble probem with the display clock.
The CPU is IMX6Q.I use the DISP0 to sent YUV to FPGA.The driver is "mxc_lcdif.c".
The image is not normal.You can look the image below .
Now I find the reason is the DISP0 pix clock.
When the pix clock pin do not connect to the FPGA.It will be 3.3vpp when output all kinds of frequency clock.
But when I connect IMX6Q via a 33R resistor to FPGA, the VPP of clock is the higher frequency the more low,and the clock offset from the GND.
Dose someone can help me to solve it?