Instruction Emulation and vcpu implementation for e500 core

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Instruction Emulation and vcpu implementation for e500 core

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amittomar
NXP Employee
NXP Employee

I have the basic idea about Hardware assisted virtualization which allows execution of most of the instruction of target(qemu) directly without emulation .but there are some

privileged instruction can not be executed directly and whenever these privileged instruction are executed by target (qemu) ,control is transferred back to Hypervisor(kvm)

which then emulates these instruction in software.

Now for e500 core, are there only two instructions(mtspr and mfspr) emulated as per e500_emulate.c?

If so how do we decide these two instruction needs to be emulated and how its implementation take place in KVM code?

Also ,It would be great if some one can tell me,how vcpu has implemented in KVM code,what is basic idea behind it?

Thanks

Amit.

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scottwood
NXP Employee
NXP Employee

mtspr/mfspr are not the only instructions that are emulated in guest mode -- and not all SPRs need to be emulated.  See Power ISA v2.06B for more details on what instructions and SPRs trap.  QEMU is not involved in instruction emulation when KVM is used.

Your final question is very broad, so it'll get a vague answer.  The basic idea is to use the hardware virtualization support to emulate a virtual CPU.  Please let me know if there's something more specific you'd like to know.

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