I investigating how one cpu core can spoil life other cpu core on p3041. And I've got unexpected results.
Core 0 task: Read-modify-write in L1 data.
Core 1 task: Copying memory areas using the DMA.
All tasks are working without OS, on bare metal, into endless loop. The memory is separate: Core 0 can't read and write memory that access for Core1 and Core 1 can't read and write memory that access for Core 0. Coherency protocol is off.
I measure minimum, maximum and average task execution time and l1 and l2 misses.
If working just Сore0: L1 data on Core0 has zero misses.
After release Core1: L1 data on Core0 has 5-7 misses and maximum task execution time grow up on 0.5%.
After disable Core1: L1 data on Core0 has zero misses again.
Anybody have idea why DMA transfer can influence on L1 data cache of CPU ?
p.s. Coherency protocol is off. Cores have a different memory bounds.