KL02 SPI SLAVE SPTEF is never set after first write

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KL02 SPI SLAVE SPTEF is never set after first write

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karkal
Contributor I

In KL02 SPI0 Slave Mode: In my design the SS is always low (i.e the KL02 as a SPI slave is always selected). I verify that the SPTEF bit is set before writing into the SPI0_D register. Then I ask the SPI master to clock. I can see that the clock is coming in but I don't see anything on the MISO line and the SPTEF bit is never set to 1 again. Am i missing something.

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davidhoover
Contributor I

I have the same problem. Although the datasheet states that "SPTEF is automatically set when all data from the transmit buffer transfers into the transmit shift register", I do not believe this to be true when CPHA and CPOL are zero.

When CPHA and CPOL are zero, in 8-bit slave mode, I can only send a single byte per chip select (the first byte). Once I have cleared SPTEF once by writing a byte, it is never set by the HW until CS rises, even though the master has shifted out many bytes. Since it never rises, it is impossible to write more data. The slave simply shifts out what it receives from the master. In my experience, it is impossible for a SPI slave to write more than one byte of data in a single SPI transaction (SS falls, transaction data, SS rises). My slave is required to send several bytes per CS, and this does not work (in my case, with a KL16Z32 and a KL25). I have not tried in 16-bit slave mode.

From KSDK 1.2, I modified the spi_loopback project so that it performs a genuine loopback test. To do this, I cut and pasted some slaveUserConfig/spiSlaveState/SPI_DRV_SlaveInit/SPI_DRV_SlaveTransfer stuff from the spi_non_blocking/slave project. I got the loopback test working between SPI0 and SPI1, and data is reliably passed from virtual master to slave and vice-versa on a FRDM-KL25Z board. But I believe this only works because the SPI Slave only sends a single byte per transaction. SS is toggled after each byte.

I also connected my KL16 SPI master to a KL25 SPI slave running the KSDK1.2 spi_polling/slave project. If my master toggles SS between every byte, the SPI slave transfers data to the master reliably. If I keep SS low during the entire block transfer, the slave only transfers the first byte.

So, it appears to me that there is a problem with the Freescale Kinetis hardware. If CPHA is set, then things appear to work better.

Sidenote: I discovered a minor software bug in the Freescale MKL16Z4.h file. The status byte of the SPI_Type structure is declared with _I instead of _IO. According to the reference manual, it is necessary to write to the SPMF bit to clear it.

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karkal
Contributor I

Hi Can you please provide an example code for KL02 SPI0 in slave mode, with interrupts and without interrupts. Thanks in advance.

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adriancano
NXP Employee
NXP Employee

Hi,

Probably you can find useful the information in this thread:

Re: FRDM-KL25Z - slow SPI clock

Also, check the SPI example for the TWR-KL25 based on Processor Expert in the CodeWarrior 10.6 installation folder:

Freescale\CW MCU v10.6\MCU\CodeWarrior_Examples\Processor_Expert\Kinetis\TWR-KL25Z48M\SPI

Hope this information can help you.

Regards,

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