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DDR3 stress tester for 4GB - failing at start of chip select 1 (CS1)

Question asked by oway on Aug 26, 2014

We used the DDR3 register programming aid V1.7 spread sheet to generate the attached .inc  file (  We then used the DDR3 stress tester tool to generate calibration values which were fed back into the and an additional calibration was performed.  After this the calibration values were used to generate the u-boot flash header file.  This seems to work great! 


The problem comes in when we try to run the DDR3 stress tester tool’s stress test function.  We find that when we run the stress test it fails with the following message.

DDR Freq: 528 MHz
t0.1: data is addr test
Address of failure: 0x90000000
Data was: 0x620d5404
But pattern  should match address


It appears that the test is failing right at the start of chip select 1 (CS1) as CS0_END is set to 0x900000000.  Furthermore, I moved CS0_END to 0x80000000, reran the stress test and it failed at 0x80000000 which I believe should be the start of CS1. 


The strange thing is that when I boot the system into Linux or Android and use the memtool I’m able to read and write memory at 0x9000000 as well as 0xFFFFFFF0.  This suggests to me that we’re able to address memory as expected. 


Any suggestions on what’s going wrong?

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