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Incorrect DDR2 configuration in TOWER defaults

Question asked by Bjoern Johannesson on Aug 25, 2014
Latest reply on Sep 15, 2014 by Bjoern Johannesson

The default DDR configuration for the tower project sets

     DDR_CR21 = 0x20040232

More specifically it clears MR1DAT0 bit E11, which means that DQS# is enabled (See DDR UM: EMR definition). This is incorrect since the Kinetis DRAM controller only supports single-ended DQS. Right??


I'm extremely surprised no one else has mentioned this in the community, probably due to the extremely poor documentation of the DRAM controller so people just give up.