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Why the CSPI slave mode receive wrong data?

Question asked by wason on Aug 22, 2014
Latest reply on Aug 25, 2014 by Yuri Muhin

Hi:

     I'm developing codes to communicating by using SPI module between two i.MX27 board .

One board works as the master/host CSPI and another works as the slave. I have writen master and slave code according the Freescale BSP's mxc_spi_test test code.    

    and my configuration is the following shape:

     MOSI is connected to MOSI

     MISO is connected to MISO

     SCK is connected to SCK

     SS is connected to SS.

     The slave  CSPI  when to receive data work as the interrupt mode.

 

      Firstly I use the loopback test to test the  CSPI. The master and slave CSPI work well, and they can write and receive same data.

      Secondly I connect two bosrd's CSPI interface. It work as :the master write some data and the slave receive its data from the master/host CSPI.

     Thirdly we can see receive data by HYPER TERMINAL.Sometimes the receive is OK.But sometimes the receive data is wrong.

 

     That is :I use SPI to write/send and receive data, the result is not correct. The 0x73 (01110011): the master/host send to the slave ,the slave received number is 0x37 (00110111) or 0x6E (01111110) and other data, the data is obviously 0x73 after shifting the data to the host from machine, the return value is the value after the shift, not the original value.

     I test another data. The master/host send to the 11114444,the slave received 1111CCCC ,CCCC or 3CCC and other data. The 1(0011 0001), 4(0011 0100) C(0100 0011),3(0011 0011). So the received data is the value after the shift.


     Every test I have run the SPI slave first and run the SPI master later. So the slaver receive first and master write data to the SPI later. The slave receive correct data after the master SPI write the data to the SPI. But sometime the slave SPI become receive wrong data and after few wrong data it becaome receive the correct data.  This wrong receive can appear often when I take the test.

 

      I donot known Why it is work incorrect? The master and slave clock polarity and phase are configured the same,the max_speed_hz = 1000000. Because I think the high speed would make CSPI work not well so I set the speed is 1000000. But I need the CSPI work as 4Mbps. The low speed are not working properly, not to mention the high speed.

 

     Follow is the HYPER TERMINAL print the message:

     The master write the data is 11114444, the slave should Data receive the 11114444.

    

Data received : 11114444

Data received : 11114444

Data received : 11114444

Data received : 11114444

Data received : 11114444

Data received : 11114444

Data received : 11114444

[fwriten data to SPI]ERROR: errno = 1, strerror = Operation not permitted

Data received : 1111CCCC

Data received : CCCC

Data received : 3CCC

Data received : CCCC

Data received : 3CCC

 

     The another test: the master send 1111444411114444,the slave should  receive 1111444411114444.

 

Data received : 1111444411114444

Data received : 1111444411114444

Data received : 1111444414444111

Data received : 111144441D4441

Data received : 1111444411114444

Data received : 1111444414444111

Data received : 11114444111144CC

Data received : CCCC3CCC

Data received : CCCCCCCC

Data received : CCCCCCCC

    

    Am I missing something here?

     Any pointers will be appreciated.

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