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Help clearing SPI TX buffers

Question asked by markosiponen on Aug 15, 2014
Latest reply on Aug 19, 2014 by Hui_Ma

I'm using a MK10FN1M0VLQ12.


I have setup DMA to transfer data to SPI2_PUSHR.


I have not enabled TX FIFO or RX FIFO for the SPI.


I see that when I enable the DMA channel the DMA immediatly transfers 2 byte. Why is this happening. Why not only one byte? Is the SPI2_PUSHR double buffered?


And another problem. When SPI chip select goes high I need to reset the DMA and also any possible outgoing data in the SPI. How can I reset the SPI TX buffers?

 

What I mean is if SR[TFFF] is 0 (TX FIFO is full) how do i get it to become 1 (TX FIFO is not full)?



Update:


Now I have tested an approach here. I have found that the following works:


    // Disable DMA MUX 0 channel first before we change anything

    DMAMUX0->CHCFG[MAIN_SPI_TX_DMA_CH] = 0;

 

 

    DMA0->CERQ = MAIN_SPI_TX_DMA_CH; // Disable DMA Request

  

    // Halt SPI

   SPI2->MCR |=  SPI_MCR_HALT_MASK;

  

    //Clear TX FIFO

    SPI2->MCR |= SPI_MCR_CLR_TXF_MASK;

  

    // Unhalt SPI

    SPI2->MCR &= (uint32_t)~(uint32_t)(SPI_MCR_HALT_MASK);

 

    Setup the DMA

    ...

 

    // Enables DMA channel and select DMA MUX Request Sources for the DMA Channel

    DMAMUX0->CHCFG[MAIN_SPI_TX_DMA_CH] = DMAMUX_CHCFG_SOURCE(21) | DMAMUX_CHCFG_ENBL_MASK; // 21 = SPI2 Transmit

 


I must halt the SPI2 and then clear the TX FIFO. Else it will not work.


Is this the correct way to do it?



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