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Stripline reference plane discontinuity in reference design

Question asked by javiermarto on Aug 11, 2014
Latest reply on Aug 11, 2014 by igorpadykov

According i.MX6 SMART DEVICE SYSTEM layout board, it uses 8 layers, my question is about the inner layers, they are striplines with a continuos GND plane in one side but in the other side they have a power layer that is broken A LOT of times (they make a lot of power islands), and some important signals cross those broken planes and that would mean a difference in Zo of the line, which mean reflections, so te integrity of the signal won't be optimal and  when we are talking about RAM data lines and other kind of sensitive lines that's a big problem, so that thats my question, i mean that's the reference design, but in my opinion is against all theory, can some one tell me if i'm wrong or gimme an awnser to orientate me in this matter please.



This is a screenshot of the internal layer 2 and the power plane, there you can see the SoC and the RAM lines.