Will tDQSQ value abnormality effect the communication with IMX6?

[王剑翰]

Last week we  tested DDR singal  of read mode. The value of  tDQSQ-Diff  is 235.14ps and that’s more than the high limit 200ps found to fail.

But the communication between the CPU(I.MX6S) and DDR3 is normal now. For CPU, this one even if NG, is no effect on communication, can we think so?

[igorpadykov · Accepted solution]

Hi 王 剑翰

value of  tDQSQ-Diff  is 235.14ps may be just caused

by placement of oscilloscope probe,

since for example for FR4 board trace length may lead to delay

about 7ps/mm.

Also for correct tDQSQ one needs to perform ddr calibration,

check sect.13 "Read DQS Delay Calibration"

AN4467  i.MX 6 Series DDR Calibration.

Best regards

chip

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

[王剑翰]

Hi Igor Padykov，

Thank you for your kindly help.

As we had performed the DDR stress test using the stress tester tool, I think the deviation should be just caused

by placement of oscilloscope probe.

So the communication between the CPU and DDR3 is normal although the tDQSQ value is not "correct". Then, we can ignore the deviation.

Do you agree with my understanding? If I am wrong, please kindly correct me, thank you!

[igorpadykov]

Hi 王 剑翰

yes, if processor works well

you can safely ignore this. Your

understanding is right.

Best regards

chip

[王剑翰]

Thank you~!