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How to interpret System Clocks table in iMX6 RMs?

Question asked by Michel Verhagen on Aug 4, 2014
Latest reply on Aug 4, 2014 by igorpadykov

What is the meaning of the System Clocks table in the iMX6 RMs?


What is the clock in the "Clock" column?


If we would change source or  frequency of for instance the AHB clock, would we need to gate all gates listed in the "Gating CCM_CCGR" bits that have ahb_clk_root in front in the "Clock Root" column? (for AHB on iMX6SDL this would mean gating AIPS_TZ1, ARM_DBG, ASRC, CAAM_SECURE_MEM, CAAM_WRAPPER_CLK, ENET, ESAI, GPU2D, GPU3D, HDMI_TX_ISFR, IPU1_IPU, MIPI_CORE, MLB, OCRAM, ROM, USBOH3 and USDHC1..4).


In iMX6SDL look at EPDC in the table. It shows:



|  Block   |        |       Clock         |  Gating CCM_CCGR   | Override CCM_CMEOR |

| Instance | Clock  |        Root         |        bits        |        bits        |


|  EPDC    | pixclk |  epdc_pix_clk_root  | ipu_di1_clk_enable |                    |


|          | aclk   |  epdc_axi_clk_root  | ipu_ipu_clk_enable |                    |

|          |        |  pxp_axi_clk_root   |                    |                    |




How does this correspond to the Clock Tree diagram, or the Clock Root Generator diagrams?


There is no mention of CCGR3 [11-10 CG5] epdc_pix_clk_enable and CCGR3 [7-6 CG3] epdc_axi_clk_enable, but I'm sure those gates affect epdc_pix_clk_root and epdc_axi_clk_root...


The information that I'm after is Clock Signal -> CGs, in other words; which gates depend on which clock signals. I know there can be more gates per clock signal. I just need a clear diagram of where those gates are (in something like a clock tree diagram), or a location where I can filter that information from (like the iMX6 Platform SDK maybe?).