There are some inconsistencies between the iMX6(SDL and DQ) 188.8.131.52.4 Clock Root Generator diagrams, 18.3 CCM Clock Tree, the 18.6 CCM Memory Map/Register Definition, and the iMX6_Platform_SDK.
As an example, take a look at the MLB_SYS_CLK_ROOT diagram (page 812 in the iMX6 SDL RM). The mux in the diagram shows:
0 --> PLL2_PFD2
1 --> DTCP
2 --> PLL2_PFD0
3 --> PLL3
The description for mlb_sys_sel in CBCMR has:
00 derive clock from axi (this is DTCP)
01 derive clock from pll3
10 307M PFD (this is PLL2_PFD0)
11 derive clock from 396M PFD (this is PLL2_PFD2)
As you can see, the source numbers are different.
The Clock Tree Diagram shows again a different picture with 0 --> PLL3
To make matters even more confusing, the iMX6 SDK calls MLB_SYS_SEL "GPU2D_CLK_SEL", and it has the following selections:
/*! @name Register CCM_CBCMR, field GPU2D_CLK_SEL[17:16] (RW)
* Selector for open vg clock multiplexer
* - 00 - derive clock from axi
* - 01 - derive clock from pll3
* - 10 - 307M PFD
* - 11 - derive clock from 396M PFD
Who is right? Up to this point I took the iMX6 SDK as the definitive source of information, but in this case it's very confusing... MLB or GPU2D?
Message was edited by: Michel Verhagen Changed: CMCMR -> CBCMR (fixed typo; there is no CMCMR reg)