There seems to be an inconsistency between the iMX6SDL CCM Clock Tree diagram (figure 18-3) and the BUS clock generation (diagram (figure 18-5).
- The BUS clock generation diagram shows a second mux (periph_clk_sel) that is not on the clock tree.
Please confirm the BUS clock diagram is correct and the Clock Tree diagram is missing this mux
- The 3rd option on the pre_periph_clk_sel mux shows "PLL2_PFD0 /2" on the BUS clock generation diagram, but on the clock tree this is "PLL2_PFD2 /2"
Please confirm the correct source is "PLL_PFD2 /2"
- There is a 3rd mux in the path; burn_in_bist
Is this a real mux, and if yes; who or what sets burn_in_bist?