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iMX6 Clock Root Generator figures wrong or not?

Question asked by Michel Verhagen on Aug 3, 2014
Latest reply on Aug 3, 2014 by igorpadykov

Hi,

 

iMX6SDL/DQ RM section 18.5.1.5.4 Clock Root Generator.

 

The figures in that chapter show the locations of the Clock Gates. The following signals show no gate (cg) in the figure, but they do have a gate according to the CCGRn registers:

 

  • PCIE
  • VDO_AXI
  • CAN_CLK
  • UART

 

 

Is this a documentation error, or does it mean these signals are really different than the others (maybe gated at a later stage)?

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