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SPI PEx component cannot use full depth of buffer?

Question asked by Jack Blather on Aug 1, 2014
Latest reply on Aug 22, 2014 by Marek Neuzil

Setting up SPI2 on the Vybrid using PEx, I noticed that the xxx_Interrupt() code that is generated by PEx doesn't take into account the depth of the FIFO. The performance is the same if the FIFO depth is set to 1 or Max (4).


I'm using PEx v10.2 with update 3.


The SPI clock is > 30 Mhz. 16-bit transfers.


Using a logic analyzer, I noticed that there is a giant 4.7 microsecond pause between words. I configured the SPI module to keep CS asserted. The component is configured so that the delays are 0.083333 microseconds.


Inspecting the code, it puts a single word in the FIFO but does not check to see if the FIFO isn't full yet. It *should* keep pumping words into the FIFO until the FIFO Full flag indicates the FIFO is full. But the ISR doesn't do that. It checks to see only if there is room in the FIFO for one more character, puts just one character in the FIFO, and then leaves the ISR.


Using the debugger, the xxx_Interrupt() ISR is called once for every byte that is transmitted. The ISR doesn't keep the FIFO filled. The watermark selection in PEx for this component doesn't seem to do anything. Also, the module is not configured to generate an interrupt when the TFFF flag indicates the FIFO is not full.


Is there a way to keep the FIFO filled and to not generate an Interrupt for every word transmitted? It seems that the idea of the FIFO is to keep the SPI module busy and the CPU as not-busy as possible by keeping interrupts to a minimum.


I have another system that has the latest PEx v10.4.1. It generates the same kind of code for the SPI xxxx_Interrupt() ISR - it is FIFO-agnostic.