SPI PEx component cannot use full depth of buffer?

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SPI PEx component cannot use full depth of buffer?

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jackblather
Senior Contributor I

Setting up SPI2 on the Vybrid using PEx, I noticed that the xxx_Interrupt() code that is generated by PEx doesn't take into account the depth of the FIFO. The performance is the same if the FIFO depth is set to 1 or Max (4).

I'm using PEx v10.2 with update 3.

The SPI clock is > 30 Mhz. 16-bit transfers.

Using a logic analyzer, I noticed that there is a giant 4.7 microsecond pause between words. I configured the SPI module to keep CS asserted. The component is configured so that the delays are 0.083333 microseconds.

Inspecting the code, it puts a single word in the FIFO but does not check to see if the FIFO isn't full yet. It *should* keep pumping words into the FIFO until the FIFO Full flag indicates the FIFO is full. But the ISR doesn't do that. It checks to see only if there is room in the FIFO for one more character, puts just one character in the FIFO, and then leaves the ISR.

Using the debugger, the xxx_Interrupt() ISR is called once for every byte that is transmitted. The ISR doesn't keep the FIFO filled. The watermark selection in PEx for this component doesn't seem to do anything. Also, the module is not configured to generate an interrupt when the TFFF flag indicates the FIFO is not full.

Is there a way to keep the FIFO filled and to not generate an Interrupt for every word transmitted? It seems that the idea of the FIFO is to keep the SPI module busy and the CPU as not-busy as possible by keeping interrupts to a minimum.

I have another system that has the latest PEx v10.4.1. It generates the same kind of code for the SPI xxxx_Interrupt() ISR - it is FIFO-agnostic.

Thanks.

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jackblather
Senior Contributor I

Upon further investigation, I slowed down the SPI clock from ~33Mhz down to a leisurely 1Mhz. At slow of a speed, the FIFO *might* be getting filled. It seems that beyond a certain speed, the way the ISR is written, it just can't keep the FIFO filled. It does it one byte at a time, instead of multiple bytes. It would seem that filling multiple bytes in the FIFO in a single ISR call would really help in the faster speeds.

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marek_neuzil
NXP Employee
NXP Employee

Hello Jack,

Thank you for reporting of this drawback of the SPI component. I am forwarding this issue to the Processor Expert development team to do further analysis.

Best Regards,

Marek Neuzil

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