PDB continuous mode timing

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PDB continuous mode timing

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billnd
Contributor IV

Running the PDB in continuous mode, how do I calculate the timebase? ie the periodicity of the PDB interrupt.

I'm on a K10, with a 92.16MHz core, 46.08MHz bus, and 23.04MHz flash.

PDB set with PRESCALER = 0, MULT = 0, MOD 1920.

With these settings I was assuming the PDB would have a cycle time of 46.08MHz / 1920 = 24.000kHz. What I actually get is a cycle time of slightly longer, so a lower frequency, something like 23.98kHz.

I had assumed that when PDBx_CNT reached MOD - 1, it wrapped to zero and continued without additional delay. This seems not to be the case.

The manual says...

     "Trigger input event to pre-trigger m = (prescaler X multiplication factor X delay m) +

          2 peripheral clock cycles"

...which suggests that maybe there could be a 2 clk delay when the wrap round occurs, if this is treated as a trigger input event every time. So investigating this gives...

MOD: 1920, PDB F: 23.98kHz

MOD: 1919, PDB F: 24.00kHz

MOD: 1918, PDB F: 24.02kHz

If there was 2 clock cycles added, I would have thought 1918 would give the closest match.

So what am I missing, any suggestions welcome.

Cheers,

Bill

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Robin_Shen
NXP TechSupport
NXP TechSupport

Hi billnd

Could you please tell us how did you measure the frequency of the PDB interrupt?

Best Regards

Robin

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Robin_Shen
NXP TechSupport
NXP TechSupport

The modulus value in MOD register, is used to reset the counter back to zero at the end of the count. If SC[CONT] bit is set, the counter will then resume a new count. Otherwise, the counter operation will cease until the next trigger input event occurs.

If it was in continuous mode, the period should be (MOD+1),so:  46.08MHz / (1920+1) = 23.9875kHz

When using systick to measure the period of PDB interrupt, we can also get the 2*(MOD+1) of core clock cycle. Just because the PDB use the bus clock which is half of core clock.

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