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DDR3 power down (sleep) issue with MPC8569E

Question asked by Niranjan Aradhya on Jul 28, 2014

Hi All,

 

We have brought MPC8569MDS referance board from Freescale, using it as a referance board and desigend our own MPC8569 custom board.

We are using MPC8569, 1066.667 MHz and 1GB DDR3 module of part No: JM1333KLU-1G Transcend make.

 

 

The below are the On-board boot switch configuration in our Custom board:

 

 

  1) QE : 01000111  ;In order to make QE to work for 533 MHz

  2) DDR3 : 01110111  ; Setting DDR3 to work at 200MHz

  3) CLK : 10001001  ; Setting CCB to work at 533.33MHz and e500 core 1066.6MHz

  4) I/O : 01110001 

  5) BOOT : 11011111  ; Boot from NOR flash and e500 to boot without waiting for configuration from external master.

  6) AUX : 11110011  ; MPC8569E acts as host processor, CCB freq is more than 333 MHz, Core clk > 1000 MHz

 

We have used Codewarrior 10.3.3 version to do memory test for DDR3 Module on our Custom board.

 

 

Issues we are facing:

If we do the Memory test using by-default Init file (.tcl) provided in the code warrior 10.3.3 directory we were getting below error and Initialization is getting failed and the DDR3 module is going to sleep mode and not waking up, resulting entire board under reset.

 

     "Failed to resume target process.

       writemem error: writemem.l 0xe0005000 0x010800fe failed."

 

we observed that "DDR Voltage is droping to zero" since ddr is going to sleep.

so we did following modification to below regsiters to continue memory test:

 

  1) D-Init bit in "DDR SDRAM Configuration 2" register is cleared

  2) "Write Leveling" and "DDR control driver register" is commented

 

  Doing Memory test using Code Warrior 10.3.3 following observation were made.

  1) DDR3 is working for 200 MHz but not for 333.33 MHz.

  2) Memory test is failing most of the times especially bus noise test is failing.

 

Questions:

  1) Could you please tell us whether we need to enable dinit bit in DDR_SDRAM_CFG_2 and write level registers or not?

  If so, what are the changes we need to do inorder to make DDR3 come out of sleep ?

  2) What is the reason for the BUS noise error and memory test failure ?

  3) Could you please tell us the changes in the Init file that we have to make in order to make the DDR3 work for 333.33 MHz.

 

We have attached the changed Initialize file which is used for our custom board along with this mail.

 

Thanks in advance

Original Attachment has been moved to: 8569MDS_init_core---Copy.tcl.zip

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