IMX53 ECSPI sending multiple bursts even though single burst is configured

[rambabu1]

Hi,

We are using a IMX53 QSB based custom board with WIN CE OS.

We have observed that even though our ECSPI driver configuration is SINGLE BURST, SPI controller is sending multiple burst till TXFIFO is empty.

Our configuration is as follows.

BURST LENGHT = 7 bits ( so 1 byte is my burst length)

DRCTL = 0 i.e. SPI_RDY is a don't care.

SMC = 0

SPI is in MASTER MODE

SSBCTL all 4 bits are 0. i.e. in MASTER MODE only ONE SPI BURST will be transferred.

Load TXFIO with multiple bytes and on XCH bit SET, we observed all the bytes in TXFIFO are being transferred in MULTIPLE BURSTS, even though it is expected to transfer only SINGLE BURST for a single XCH bit set.

If we make TXFIFO have only one byte at a time, then as expected only one burst is exchanged as TXFIFO will become empty after 1 byte exchange, 

Please let us know if any body faced this issue.

We need to know whether is this a problem from IXM53 controller or any configuration mismatch.

Thanks,

Rambabu

[Bio_TICFSL]

It seems this is only happening when SS CTRL is active(high) on the correspond channel. This is not a normal behavior, however we don't have a workaround for it. AdeneoEmbedded is supporting Wince for QSB, maybe the have a work around on it.