We are developing a custom board based on the imx6sl evolution kit. We are going to use 2 ddr3 through single chip select. both ddr are 256 MB size.
Now for better routing purpose, We have swapped the ddr data lines coming from the processor.
data byte 1 from processor is connected to dql0 to dql7 on 1st ddr. but this line are swapped for efficient routing like, d6 from processor is connected to dql0 of ddr etc.
data byte 2 from processor id connected to 2nd ddr's dql0 to dql7. similarly data byte3 from processor connected to dqu0 to dqu7.
We have also swapped the dqs lines between different bytes. like dqs0 is for byte1, dqs2 is for byte2, dqs1 is for byte3 etc.
So, for dqs and data lines swapping what changes we need to do in ddr controller registers?
Is this approach fine?