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K60 FlexBus 16-bit data, 10-bit address to CPLD

Question asked by Abby Chen on Jul 22, 2014
Latest reply on Jul 30, 2014 by Abby Chen

Hi,

I use K60 FlexBus to read/write CPLD in 16-bit data and 10-bit address mode.

 

HW setting:

//FlexBus

//Address

PORTB_PCR20 = PORT_PCR_MUX(5);           //  fb_ad[31] - FB_XA15

PORTB_PCR21 = PORT_PCR_MUX(5);           //  fb_ad[30] - FB_XA14

PORTB_PCR22 = PORT_PCR_MUX(5);           //  fb_ad[29] - FB_XA13

PORTB_PCR23 = PORT_PCR_MUX(5);           //  fb_ad[28] - FB_XA12

PORTC_PCR12 = PORT_PCR_MUX(5);           //  fb_ad[27] - FB_XA11

PORTC_PCR13 = PORT_PCR_MUX(5);           //  fb_ad[26] - FB_XA10

PORTC_PCR14 = PORT_PCR_MUX(5);           //  fb_ad[25] - FB_XA9

PORTC_PCR15 = PORT_PCR_MUX(5);           //  fb_ad[24] - FB_XA8

PORTB_PCR6  = PORT_PCR_MUX(5);           //  fb_ad[23] - FB_XA7

PORTB_PCR7  = PORT_PCR_MUX(5);           //  fb_ad[22] - FB_XA6

PORTB_PCR8  = PORT_PCR_MUX(5);           //  fb_ad[21] - FB_XA5

PORTB_PCR9  = PORT_PCR_MUX(5);           //  fb_ad[20] - FB_XA4

PORTB_PCR10 = PORT_PCR_MUX(5);          //  fb_ad[19] - FB_XA3

PORTB_PCR11 = PORT_PCR_MUX(5);           //  fb_ad[18] - FB_XA2

PORTB_PCR16 = PORT_PCR_MUX(5);           //  fb_ad[17] - FB_XA1

PORTB_PCR17 = PORT_PCR_MUX(5);           //  fb_ad[16] - FB_XA0

//Data

PORTB_PCR18 = PORT_PCR_MUX(5);           //  fb_ad[15] - FB_XD15

PORTC_PCR0  = PORT_PCR_MUX(5);           //  fb_ad[14] - FB_XD14

PORTC_PCR1  = PORT_PCR_MUX(5);           //  fb_ad[13] - FB_XD13

PORTC_PCR2  = PORT_PCR_MUX(5);           //  fb_ad[12] - FB_XD12

PORTC_PCR4  = PORT_PCR_MUX(5);           //  fb_ad[11] - FB_XD11

PORTC_PCR5  = PORT_PCR_MUX(5);           //  fb_ad[10] - FB_XD10

PORTC_PCR6  = PORT_PCR_MUX(5);           //  fb_ad[9]  - FB_XD9

PORTC_PCR7  = PORT_PCR_MUX(5);           //  fb_ad[8]  - FB_XD8

PORTC_PCR8  = PORT_PCR_MUX(5);           //  fb_ad[7]  - FB_XD7

PORTC_PCR9  = PORT_PCR_MUX(5);           //  fb_ad[6]  - FB_XD6

PORTC_PCR10 = PORT_PCR_MUX(5);           //  fb_ad[5]  - FB_XD5

PORTD_PCR2  = PORT_PCR_MUX(5);           //  fb_ad[4]  - FB_XD4

PORTD_PCR3  = PORT_PCR_MUX(5);           //  fb_ad[3]  - FB_XD3

PORTD_PCR4  = PORT_PCR_MUX(5);           //  fb_ad[2]  - FB_XD2

PORTD_PCR5  = PORT_PCR_MUX(5);           //  fb_ad[1]  - FB_XD1

PORTD_PCR6  = PORT_PCR_MUX(5);           //  fb_ad[0]  - FB_XD0

//Control signals

    PORTB_PCR19 = PORT_PCR_MUX(5);           // fb_oe_b

    PORTC_PCR11 = PORT_PCR_MUX(5);           // fb_rw_b 

    PORTD_PCR1  = PORT_PCR_MUX(5);           // fb_cs0_b  to CPLD

    PORTC_PCR18 = PORT_PCR_MUX(5);    // fb_cs2/b

    PORTD_PCR0  = PORT_PCR_MUX(5);           // fb_ale

    PORTC_PCR3  = PORT_PCR_MUX(5);    // CLKOUT

 

FlexBus initial code:

#define CPLD_ADDR   (*(vuint16*)(0xA0000000))

FB_CSAR0 = (uint32)&CPLD_ADDR;

FB_CSMR0  =   FB_CSMR_BAM(7)  //Set base address mask for address space

                         | FB_CSMR_V_MASK ;   //Enable CS signa

                     

FB_CSCR0  =   FB_CSCR_PS(2)      // 16-bit port

             | FB_CSCR_AA_MASK    // auto-acknowledge

             | FB_CSCR_ASET(0x1)  // assert chip select on second clock edge after address is asserted

             | FB_CSCR_WS(0x1)    // 1 wait state - may need a wait state depending on the bus speed

             | FB_CSCR_BLS_MASK;

 

Write to CPLD:

uint16 CPLDdata = 0x1234;

*(vuint16*)(&CPLD_ADDR) = CPLDdata; 

 

Q1:

If I want to write the next 16-bit data to the next address, the CPLD_ADDR will plus 2 or 1?
For example: 1st address is 0xA0000000, 2nd address will be 0xA0020000 or 0xA0010000?

If plus 2, this means  one addree = 8-bit data?

 

Q2:

In HW connection,(16-bit data mode)

Which connection is right?

1. FB_XA[0-9] <-> CPLD's address[0-9]

2. FB_XA[1-10]<-> CPLD's address[0-9]

 

Thank you.

Abby

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