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RMII on IMX6Q

Question asked by j b on Jul 21, 2014
Latest reply on Dec 20, 2014 by cao ping

I can't get ethernet RMII interface to work on custom hardware with an IMX6Q and a LAN8720A. 

 

Here are my schematics:

 

lan8720a.pngenet_cpu.png

I have made the following changes to u-boot and the kernel. (Following Fugan Duan's patches Re: iMX6 RGMII + ENET_REF_CLK/ENET_TX_CLK)

dtra3 is the name of my custom hardware.

Here I'll just show my changes to u-boot to make the RMII interface work.  I'm using GPIO 16 as clock output for the phy.

------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

u-boot/board/freescale/mx6q_dtra3/mx6q_dtra3.c

 

#define DTRA3_FEC_PHY_RESET IMX_GPIO_NR(6, 7)

 

#define ANATOP_PLL_LOCK                 0x80000000 /*change 1*/

#define ANATOP_PLL_ENABLE_MASK          0x00002000

#define ANATOP_PLL_BYPASS_MASK          0x00010000 /*change 3*/

#define ANATOP_PLL_PWDN_MASK            0x00001000 /*change 2*/

#define ANATOP_PLL_HOLD_RING_OFF_MASK   0x00000800

#define ANATOP_SATA_CLK_ENABLE_MASK     0x00100000

#define ANATOP_FEC_PLL_ENABLE_MASK      0x00002000 /*change 4*/

 

static int setup_fec(void)

{

  u32 reg = 0;

  s32 timeout = 100000;

    /*

    * get enet tx reference clk from internal clock from anatop

    * GPR1[21] = 1

    */

    reg =  readl(IOMUXC_BASE_ADDR + 0x4);

    reg |= (0x1 << 21);

    writel(reg, IOMUXC_BASE_ADDR + 0x4);

 

 

  /* Enable PLLs */

  reg = readl(ANATOP_BASE_ADDR + 0xe0); /* ENET PLL */

  if ((reg & ANATOP_PLL_PWDN_MASK) || (!(reg & ANATOP_PLL_LOCK))) {

  reg &= ~ANATOP_PLL_PWDN_MASK;

  writel(reg, ANATOP_BASE_ADDR + 0xe0);

  while (timeout--) {

  if (readl(ANATOP_BASE_ADDR + 0xe0) & ANATOP_PLL_LOCK)

  break;

  }

  if (timeout <= 0)

  return -1;

  }

 

  /* Enable FEC clock */

  reg |= ANATOP_FEC_PLL_ENABLE_MASK;  //reg &= ~ANATOP_FEC_PLL_ENABLE_MASK;

  reg &= ~ANATOP_PLL_BYPASS_MASK;

  writel(reg, ANATOP_BASE_ADDR + 0xe0);

  return 0;

}

 

iomux_v3_cfg_t enet_pads[] = {

  MX6Q_PAD_ENET_MDIO__ENET_MDIO,

  MX6Q_PAD_ENET_MDC__ENET_MDC,

  MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN,

  MX6Q_PAD_ENET_RX_ER__ENET_RX_ER,

  MX6Q_PAD_ENET_TX_EN__ENET_TX_EN,

  MX6Q_PAD_ENET_RXD0__ENET_RDATA_0,

  MX6Q_PAD_ENET_RXD1__ENET_RDATA_1,

  MX6Q_PAD_ENET_TXD0__ENET_TDATA_0,

  MX6Q_PAD_ENET_TXD1__ENET_TDATA_1,

  MX6Q_PAD_NANDF_ALE__GPIO_6_8, /* wired to CPU_INT_B from the int/refclk0 pin on the LAN8720 */

  MX6Q_PAD_NANDF_CLE__GPIO_6_7, /* output connected to RESET_B to the rst pin on the LAN8720 */

  MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT, /* wired to ENET_REF_CLK_50M to the clkin pin on the LAN8720 */

};

 

void enet_board_init(void){

...

gpio_direction_output(DTRA3_FEC_PHY_RESET, 0);

udelay(10000);

gpio_direction_output(DTRA3_FEC_PHY_RESET, 1);

mxc_iomux_set_gpr_register(1, 21, 1, 1);

...

}

 

include/asm-arm/arch-mxt6/mx6_pins.h

 

#define MX6Q_ENET_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)

 

#define _MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT \

IOMUX_PAD(0x0618, 0x0248, 2 | IOMUX_CONFIG_SION, 0x083C, 1, 0)


And finally set MUX_PADS_CTRL(MX6Q_ENET_PAD_CTRL) on all the ENET pads.


include/configs/mx6q_dtra3.h

#define CONFIG_FEC0_PHY_ADDR 1

------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

 

Below I"ve pasted my Uboot output (with MII_DEBUG and ET_DEBUG set):

 

U-Boot 2009.08 (Jul 21 2014 - 15:23:54)

 

 

CPU: Freescale i.MX6 family TO1.2 at 792 MHz

Thermal sensor with ratio = 185

Temperature:   39 C, calibration data 0x5914e57d

mx6q pll1: 792MHz

mx6q pll2: 528MHz

mx6q pll3: 480MHz

mx6q pll8: 50MHz

ipg clock     : 66000000Hz

ipg per clock : 66000000Hz

uart clock    : 80000000Hz

cspi clock    : 60000000Hz

ahb clock     : 132000000Hz

axi clock   : 264000000Hz

emi_slow clock: 132000000Hz

ddr clock     : 528000000Hz

usdhc1 clock  : 198000000Hz

usdhc2 clock  : 198000000Hz

usdhc3 clock  : 198000000Hz

usdhc4 clock  : 198000000Hz

nfc clock     : 24000000Hz

Board: i.MX6Q-DTRA-3: DTRA3 Board: 0x63e12 [POR]

Boot Device: SD (2)

I2C:   ready

DRAM:   1 GB

MMC:   FSL_USDHC: 0,FSL_USDHC: 1,FSL_USDHC: 2,FSL_USDHC: 3

In:    serial

Out:   serial

Err:   serial

Net:   FEC0: rxbd 27603020 txbd 27603060 ->276030a0

got MAC address from IIM: 00:00:00:00:00:00

enet_board_init: dtra3

FEC0 [PRIME]

Hit any key to stop autoboot:  0

DTRA-3 U-Boot > ping 192.168.1.2

FEC: Link is Up 782d

100Mbps

Using FEC0 device

mxc_fec.c[614] fec_send: cycles: 1    status: c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: 2c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: 2c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: 2c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: 2c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: 2c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: 2c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: 2c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: 2c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: 2c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: 2c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: 2c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: 2c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: 2c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: 2c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: 2c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: 2c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: 2c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: 2c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: 2c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: 2c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: 2c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: 2c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: 2c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: 2c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: c00  retry cnt: 0

mxc_fec.c[614] fec_send: cycles: 1    status: 2c00  retry cnt: 0

ping failed; host 192.168.1.2 is not alive

DTRA-3 U-Boot > mii dump

Error reading from the PHY addr=00 reg=00

 

Other observations:

The valid link LED and activity LED both come up and the activity LED blinks during the ping operation. ENET_REF_CLK_50M is up and looks good, and ENET_MDC comes up during the ping command.  Otherwise it's not up.  With a scope I can see activity on all the lines RXD0, RXD1, CRS_DV, ENET_MDIO, TX_EN, TXD0 and TXD1 during the ping command.

 

Can anybody help.  Specifically why does the mii dump command throw and error?

Outcomes