Where are MPU_EARn/MPU_EDRn (n=5 to 7)

[yasuhikokoumoto]

Hi, all.
I have a question about the Kinetis K70 MPU (Memory Protection Unit). Regarding SDRAM, any MPU slave ports are not assigned. I wonder to where the error information would be stored because there are only five registers (i.e. MPU_EAR/MPU_EDR) according to the other device slave ports. Although there are 8 slave port bit fields in MPU_CESR[SPERR], why are not there MPU_EAR5/MPU_EDR5 to MPU_EAR7/MPU_EDR7 in the K70 reference manual?

Yasuhiko Koumoto

[yasuhikokoumoto]

Hello Kan-san,

thank you very much.

I understood well.

However let me ask one more question.

Does it mean that the K70 reference mamual (K70P256M150SF3RM.pdf) downloaded from the freescale site would be incorrect, because of no description of MPU_EAR5/MPU_EAR5 to MPU_EAR7/MPU/EDR7?

Are those located in rhe address space between 0x4000_D038 to 0x4000d050?

Best regards,

Yasuhiko Koumoto.

[Kan_Li · Accepted solution]

Hi Yasuhiko Koumoto,

I have got confirmation from our Apps team, this is an error in the manual (which then caused the registers to be left out of the header file). The docs team is actually working on a refresh of the manual. I think such issue would be fixed when it has been updated.

Have a great day,
B.R
Kan

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[yasuhikokoumoto]

Hi Kan-san,

thank you for your information.

I can close this issue.

Best regards,

Yasuhiko Koumoto.

[yasuhikokoumoto]

I have gotten an answer from Freescale Japan guy. That is, as for the MPU error of SDRAM, the error information will be stored into one of MPU_EAR0/MPU_EDR0 to MPU_EAR4/MPU_EDR4 in the K70 case. Because those MPU slave port numbers are assigned into the other devices, we should distinguish whether the error information will be for one of SDRAM by reading the error address of MPU_EAR0 to MPU_EAR4.

I wonder why K70 specification is so, although the address spaces of MPU_EAR5/MPU_EDR5 to MOU_EAR7/MPU_EDR7 will be reserved. Is it really true?

I would like to get more comments from the other persons.

Yasuhiko Koumoto.

[Kan_Li]

Hi Yasuhiko Koumoto,

The MPU on this part has 8 slave monitors as follows (NOTE the DRAMC has three ports and the access from the 8 masters are partitioned by master number across these three ports to spread out the DRAMC bandwidth load, so for DRAM access, s5 - dramc - monitors all accesses to DRAMC from M0, M1, M2 // s6 - dramc - monitors all accesses to DRAMC from M4, M6 // s7 - dramc - monitors all accesses to DRAMC from M3, M5, M7 //

The MPU has error registers for all the slave ports it monitors. That is, there are MPU_EARn 0-7, MPU_EDRn 0-7, etc. registers.

Have a great day,
B.R
Kan

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