We have a mature product that was developed on CW7. We've ported it over to CW10.4, and have found that some boards, identical in measured 25Mhz xtal input, are running about 20% slower. 40Mhz instead of 50Mhz.
This is causing the uart baud rate calculations to be wrong among other things.
Below is the pll initialization function. I've checked the LOCK bit in SYNSR and it indicates that the PLL is locked.
MCF_CLOCK_CCHR =0x05; // The PLL pre divider - 25MHz / 5 = 5MHz
/* The PLL pre-divider affects this!!!
* Multiply 25Mhz reference crystal /CCHR by 10 to acheive system clock of 50Mhz --> MCF_CLOCK_SYNCR_MFD(3)
MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(3) | MCF_CLOCK_SYNCR_CLKSRC| MCF_CLOCK_SYNCR_PLLMODE | MCF_CLOCK_SYNCR_PLLEN ;
while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK))
I've tried erasing the chip completely and then re-programming to no avail. If I load up one of the S19 files that was generated with CW7, then there are no issues with any of the boards.
chip markings are different only in the third line:
Any ideas on how to correct this would be greatly appreciated!