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P2041 DDR RCW MEM_PLL_RAT incorrect

Question asked by chris bradbrook on Jul 18, 2014
Latest reply on Jul 25, 2014 by chris bradbrook

Hello,

I am having some trouble setting up the PLL for the DDR controller on the P2041. 

The RCW memory map in the users manual has MEM_PLL_CFG and MEM_PLL_RAT mapped to

bits 8-9 and 10-14.  When using this mapping, the controller frequency is not what

is expected.  I found that by shifting the two fields one bit to the left

MEM_PLL_CFG(to bits 7-8) and MEM_PLL_RAT(to bits 9-13)in the RCW memory map corrects the

problem(or seems to).

I'm just wondering anyone else has encountered this problem and if this is the correct fix.

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