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Recommended layout for 64-bit ECC DDR3L with i.mx6Q?

Question asked by Andrew Kohlsmith on Jul 17, 2014
Latest reply on Jul 24, 2014 by Andrew Kohlsmith

I've been going over the hardware development guide and the section on DDR3 routing is especially informative. It appears that routing by byte lane and using fly-by routing with write levelling is probably the best approach for layout, but the documentation stops short of giving recommendations for a 4GB, 5-chip DDR3L layout (4 devices + 1 for ECC).

 

Has anyone done this kind of layout with an i.MX6? Do you have recommendations on the layout? Are there any known gotchas or things to avoid when doing an ECC layout with the i.MX6?

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