I have a question about the I2C module's clock divider field I2C0_F while using Processor Expert. I was able to successfully set the SCL clock rate to 100kHz by setting the internal frequency to 24MHz and my 0-2 divider bits to 111 and my 3-5 divider bits to 011. I understand that by selecting my internal frequency I'm actually setting the mul bits (bits 6-7), and that since my bus frequency is 24MHz the mul bits were set to 00 by processor expert to yield a mul divider value of 1.
What is puzzling me is the 0-2 divider bits and the 3-5 divider bits. The overall divider value needed to be 240 to bring the 24MHz down to 100kHz. I set them where I thought they might need to go, but that didn't seem to work. I couldn't figure out the logic of these bits so I simply began randomly setting and clearing bits until I got the SCL frequency set to 100kHz.
I've read Freescale's AN4342 and on page 4 of that document they give an example of three different ways to achieve the same SCL frequency using three different values. I can follow it until the 0-2 and 3-5 divider values need to be beyond the range possible with just six bits. Are these bits some kind of offset from their normal placement, or are these bits multiples of one another with an offset? Am I making this too complicated?
I should just move on knowing I have the proper values set to make things work, but this is really bugging me. Can anyone explain how these bits work?