We have a high-resolution LVDS LCD that needs a pixel clock of 74Mhz. However, I noticed that the LTIB 4.1.0 BSP U-boot appears to only support a pixel rate of 65Mhz. The following line in mx5q_sabresd.c is used to initialize the Frame buffer
ret = ipuv3_fb_init(&PK070HD30, di, IPU_PIX_FMT_RGB24, DI_PCLK_LDB, 65000000);
But in addition to changing the frequency there one must update the PLL settings somewhere I'm guessing. The clock parent needs to run at 7x the pixel clock (528Mhz) if I understand correctly. I tried changing the pll2_pfd_352M divider/multipier in mx6q_sabresd.c, but was not able to generate the desired frequency. What's missing ?
Thanks in advance